鈥?/div>
Fast access time:
(Access time)
3.0V operation
CXK5T8512TM/TN-10LLX 100ns (Max.)
CXK5T8512TM/TN-12LLX 120ns (Max.)
3.3V operation
CXK5T8512TM/TN-10LLX 85ns (Max.)
CXK5T8512TM/TN-12LLX 100ns (Max.)
Low standby current:
14碌A (Max.)
Low data retention current: 12碌A (Max.)
Low power data retention: 2.0V (Min.)
Package line-up
CXK5T8512TM
8mm
脳
20mm 32 pin TSOP package
CXK5T8512TN
8mm
脳
13.4mm 32 pin TSOP package
Block Diagram
CXK5T8512TM
32 pin TSOP (Plastic)
CXK5T8512TN
32 pin TSOP (Plastic)
Preliminary
For the availability of this product, please contact the sales office.
A15
A13
A8
A11
A9
A7
A6
A5
A14
A12
Buffer
Row
Decoder
Memory
Matrix
1024
脳
512
V
CC
GND
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
A4
A3
A10
A0
A2
A1
OE
Buffer
I/O Gate
Column
Decoder
Buffer
WE
CE1
CE2
I/O Buffer
I/O1
I/O8
Function
65536-word
脳
8-bit static RAM
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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