鈥?/div>
-12LLX
120ns (Max.)
3.3V operation -10LLX
85ns (Max.)
-12LLX
100ns (Max.)
Low standby current:
28碌A(chǔ) (Max.)
Low data retention current: 24碌A(chǔ) (Max.)
Low power data retention:
2.0V
(Min.)
Package 8mm
脳
13.4mm 32 pin TSOP package
Row
Decoder
Memory
Matrix
1024
脳
1024
V
CC
GND
Function
131072-word
脳
8-bit static RAM
Structure
Silicon gate CMOS IC
A6
A5
A4
A3
A2
A1
A0
OE
Buffer
I/O Gate
Column
Decoder
Buffer
WE
CE1
CE2
I/O Buffer
I/O1
I/O8
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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