鈥?/div>
Package line-up
Dual Vcc/Vss
CXK5B81020J
CXK5B81020TM
400mil 32pin SOJ package
400mil 32pin TSOP package
12ns (Max.)
10mA (Max.)
864mW (Max.)
Function
131072 word
脳
8-bit static RAM
Structure
Silicon gate Bi-CMOS IC
CXK5B81020J
32 pin SOJ (PIastic)
CXK5B81020TM
32 pin TSOP (PIastic)
Block Diagram
A15
A16
A9
A8
A13
A14
A11
A10
Buffer
Row
Decoder
Memory
Matrix
256
脳
4096
Pin Configuration
(Top View)
Pin Description
Symbol
A0 to A16
I/O1 to I/O8
CE
WE
OE
V
CC
GND
NC
Description
Address input
Data input
Chip enable input
Write enable input
Output enable input
+3.3V power supply
Ground
No connection
A3
Vcc
A2
A1
A0
CE
GND
1
2
3
4
5
32
A4
31
A5
30
A6
29
A7
28
OE
27
I/O8
26
I/O7
25
GND
24
Vcc
23
I/O6
22
I/O5
2
A8
1
20
A9
19
A10
18
A11
17
A12
I/O1
6
I/O2
7
Vcc
8
GND
9
A12
A5
A4
A3
A0
A2
A1
A6
A7
Buffer
I/O Gate
Column
Decoder
I/O3
1
0
I/O4
11
WE
12
A16
13
A15
14
A14
15
A13
16
WE
OE
CE
I/O
Buffer
I/O1 I/O8
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any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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