鈥?/div>
Package line-up
Dual Vcc/Vss
CXK5B18120TM
400mil 44pin TSOP Package
Block Diagram
A14
A15
A9
A8
A12
A13
A11
A10
Buffer
Row
Decoder
Memory
Vcc
Matrix
256
脳
4608
Pin configuration
(Top View)
A4
1
A3
2
A2
3
A1
4
A0
5
CE
6
GND I/O1
7
I/O2
8
I/O3
9
I/O4
1
Vcc
11
I/O Gate
Column
Decoder
GND
12
I/O5
13
I/O6
14
I/O7
15
I/O8
16
I/O9
17
WE
18
A15
19
I/O
Buffer
A14
20
A13
21
A12
22
0
44
A5
43
A6
42
A7
41
OE
40
UB
39
LB
38
I/O18
37
I/O17
36
I/O16
35
I/O15
34
GND
33
Vcc
32
I/O14
31
I/O13
30
I/O12
29
I/O11
28
I/O10
27
NC
26
A8
25
A9
24
A10
23
A11
Pin Description
Symbol
Description
A0 to A15 Address input
I/O1
to I/O9
Data input output
(lower byte I/O)
I/O10
Data input output
to I/O18 (upper byte I/O)
CE
WE
OE
LB
UB
Vcc
GND
NC
Chip enable input
Write enable input
Output enable input
Lower byte select input
Upper byte select input
+3.3V Power supply
Ground
No connection
A5
A4
A3
A0
A2
A1
A6
A7
UB
LB
WE
OE
CE
I/O1 I/O18
Buffer
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any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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