鈥?/div>
-55LL
55ns (Max.)
-70LL
70ns (Max.)
-10LL
100ns (Max.)
Low standby current
CXK591000TM/YM/M
-55LL/70LL/10LL
24碌A (Max.)
Low data retention current
CXK591000TM/YM/M
-55LL/70LL/10LL
14碌A (Max.)
Single +5V supply: 5V 鹵 10%.
Low voltage date retention: 2.0V (Min.)
Broad package line-up
CXK591000TM/YM
8mm
脳
20mm 32 pin TSOP Package
CXK591000M
525mil 32 pin SOP
Package
Block Diagram
A10
A11
A9
A8
A13
A15
A16
A14
A12
A7
Buffer
Row
Decoder
Memory
Matrix
1024
脳
1152
V
CC
GND
A6
A5
A4
A3
A2
A1
A0
OE
WE
CE1
CE2
Buffer
I /O Gate
Column
Decoder
Function
131072 word
脳
9 bit static RAM
Structure
Silicon gate CMOS IC
Buffer
I /O Buffer
I/O1 I/O9
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any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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