鈥?/div>
(Access time)
55ns (Max.)
70ns (Max.)
Block Diagram
A15
A13
A8
A11
A9
A7
A6
A5
A14
A12
CXK58512TM
32 pin TSOP (Plastic)
CXK58512M
32 pin SOP (Plastic)
Buffer
Row
Decoder
Memory
Matrix
1024
脳
512
V
CC
-10LL
100ns (Max.)
Low standby current
10碌A (Max.)
Low data retention current
6碌A (Max.)
Single +5V supply: +5V 鹵 10%
Low voltage data retention: 2.0V (Min.)
Broad package line-up
CXK58512TM 8mm
脳
20mm 32 pin TSOP package
CXK58512M
525mil 32 pin SOP Package
GND
A4
A3
A10
A0
A2
A1
OE
Buffer
I/O Gate
Column
Decoder
Function
65536-word
脳
8 bit static RAM
Structure
Silicon gate CMOS IC
Buffer
WE
CE1
CE2
I/O Buffer
I/O1
I/O8
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any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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