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CXD2508AR Datasheet

  • CXD2508AR

  • CD Digital Signal Processor

  • 856.24KB

  • 49頁

  • SONY   SONY

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CXD2508AQ/AR
CD Digital Signal Processor
For the availability of this product, please contact the sales office.
Description
The CXD2508AQ/AR is a digital signal processor
for CD players and is equipped with built-in digital
filters, no-sound data detection circuit, and 1-bit
DAC.
Features
DSP block
鈥?/div>
Digital PLL
鈥?/div>
EFM frame sync protection
鈥?/div>
SEC strategy-based error correction
鈥?/div>
Subcode demodulation, CRC checking
鈥?/div>
Digital spindle servo
鈥?/div>
Servo auto sequencer
鈥?/div>
Asymmetry compensation circuit
鈥?/div>
Digital audio interface output
鈥?/div>
16K RAM
鈥?/div>
Double-speed playback capability
鈥?/div>
New microcomputer interface circuit
Digital filter, DAC block
鈥?/div>
Double-speed playback capability
鈥?/div>
Digital de-emphasis
鈥?/div>
Digital attenuation
鈥?/div>
No-sound data detection circuit
鈥?/div>
4 Fs oversampling filter
鈥?/div>
Secondary
鈭嗏垜
noise shaper
鈥?/div>
PWM-system pulse conversion output
CXD2508AQ
80 pin QFP (Plastic)
CXD2508AQ
80 pin QFP (Plastic)
CXD2508AQ
80 pin QFP (Plastic)
CXD2508AR
80 pin LQFP (Plastic)
Applications
CD players
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
鈥?/div>
Supply voltage V
DD
鈥?.3 to 7.0
V
鈥?/div>
Input voltage
V
I
鈥?.3 to 7.0
V
鈥?/div>
Input voltage
V
IN
Vss鈥?.3V (min.) V
DD
+0.3 (max.) V
鈥?/div>
Output voltage V
O
鈥?.3 to 7.0
V
鈥?/div>
Storage temperature
Tstg
鈥?0 to 125
擄C
鈥?/div>
Supply voltage variation
V
SS
鈥揂V
SS
鈥?.3V (min.) +0.3V (max.)
V
DD
鈥揂V
DD
鈥?.3V (min.) +0.3V (max.)
Recommended Operating Conditions
鈥?/div>
Supply voltage V
DD Note)
4.5 to 5.5V
(double-speed playback)
3.5 to 5.5V
(normal-speed playback)
3.4 to 5.5V
(low power consumption
or special playback mode)
鈥?/div>
Operating temperature
Topr
鈥?0 (min.) 75 (max.)
擄C
Note)
V
DD
(min.) is varied by the playback speed and built-in
VCO in the CXD2508AQ/AR. 4.5V is the value using the
VCO which generates the slower frequency in double-
speed playback. The table below shows the V
DD
(min.)
for each condition.
V
DD
(min.) [V]
Playback
speed
脳
2
脳
1
脳
1
鈭?/div>
VCO
VCO
DAC block
high-speed normal-speed
3.40
3.40
3.40
4.50
3.50
3.40
3.40
3.40
3.40
鈭?/div>
When the internal operation of the LSI is set to double-
speed mode and the crystal oscillation frequency is
halved, normal-speed playback results.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
鈥?鈥?/div>
E94602A54-ST

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