C8051F331
25 MIPS, 8 kB Flash, 20-Pin Mixed-Signal MCU
Analog Peripherals
Comparator
High-Speed 8051 碌C Core
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Programmable hysteresis and response time
Configurable to generate interrupts or reset
Low current (0.4 碌A(chǔ))
Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
Up to 25 MIPS throughput with 25 MHz clock
Expanded interrupt handler
768 bytes data RAM
8 kB Flash; in-system programmable in 512 byte sectors (512 bytes are
reserved)
17 port I/O; all are 5 V tolerant
Hardware SMBus鈩?(I2C鈩?compatible), SPI鈩? and UART serial ports
available concurrently
Programmable 16-bit counter/timer array with three capture/compare
modules, WDT
4 general-purpose 16-bit counter/timers
Real-time clock mode using PCA or timer and external clock source
Two internal oscillators:
Memory
On-Chip Debug
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On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
Provides breakpoints, single stepping, watchpoints
Inspect/modify memory, registers, and stack
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
Digital Peripherals
Supply Voltage: 2.7 to 3.6 V
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Typical operating current: 6.4 mA at 25 MHz
9 碌A(chǔ) at 32 kHz
Typical stop mode current: <0.1 碌A(chǔ)
Clock Sources
Temperature Range: 鈥?0 to +85 擄C
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25 MHz, 2% accuracy supports UART operation
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80 kHz low frequency, low-power
External oscillator: Crystal, RC, C, or Clock (1 or 2 pin modes)
Can switch between clock sources on-the-fly
20-pin QFN (standard lead and lead-free packages)
Lead-free package: C8051F331-GM
Standard package: C8051F331
Package
Ordering Part Numbers
Port 0
Latch
UART
Timer 0,
1, 2, 3
3-Chnl
PCA/
WDT
SMBus
SPI
Port 1
Latch
P
1
D
r
v
P
0
D
r
v
X
B
A
R
VDD
GND
Analog/Digital
Power
8 kB
FLASH
256 Byte
SRAM
512 Byte
XRAM
P0.0/VREF
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVST
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
C2D
Debug HW
Reset
Brown-
Out
RST/C2CK
POR
External
Oscillator
Circuit
8
0
5
1
XTAL1
XTAL2
24.5 MHz (2%)
Internal
Oscillator
80 kHz
Internal
Oscillator
System Clock
C
o
SFR Bus
r
e
CP0
+
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Port 2
Latch
C2D
P2.0/C2D
Small Form Factor
Copyright 漏 2005 by Silicon Laboratories
5.5.2005
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