C8051F317
25 MIPS, 16 kB Flash, 24-Pin Mixed-Signal MCU
Analog Peripherals
Two Comparators
High-Speed 8051 碌C Core
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Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
Up to 25 MIPS throughput with 25 MHz system clock
Expanded interrupt handler
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Programmable hysteresis and response time
Configurable to generate interrupts or reset
Low current (<0.5 碌A(chǔ))
POR/Brown-Out Detector
Memory
1280 bytes data RAM (1024 + 256)
16 kB Flash; in-system programmable in 512-byte sectors (512 bytes
are reserved)
On-Chip Debug
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On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
Provides breakpoints, single stepping, watchpoints
Inspect/modify memory, registers, and stack
Digital Peripherals
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21 port I/O; all are 5 V tolerant
1 Enhanced Hardware SMBus鈩?(I2C鈩?compatible) and UART serial
port
Programmable 16-bit counter/timer array with three capture/compare
modules, WDT
5 general-purpose 16-bit counter/timers
Dedicated watchdog timer; bidirectional reset
Real-time clock mode for maximum power saving
Superior performance to emulation systems using ICE-chips, target pods,
and sockets
Supply Voltage: 2.7 to 3.6 V
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Typical operating current: 5 mA at 25 MHz
Typical: 11 碌A(chǔ) at 32 kHz
Target stop mode current: <0.1 碌A(chǔ)
Temperature Range: 鈥?0 to +85 擄C
Clock Sources
Internal oscillator: 24.5 MHz, 2% accuracy supports UART operation
External oscillator: Crystal, RC, C, or Clock (1 or 2 pin modes)
Can switch between clock sources on-the-fly
Package
24-pin QFN (lead-free package)
VDD
Analog/Digital
Power
Port 0
Latch
Port 1
Latch
P
0
D
r
v
C
R
O
S
S
B
A
R
P
1
D
r
v
P
2
D
r
v
P
3
D
r
v
CP0
GND
UART
C2D
P0.0/VREF
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVST
P0.7
Debug HW
Reset
/RST/C2CK
POR
Brown-
Out
8
0
5
1
16 kB
FLASH
256 byte
SRAM
1 kB
SRAM
Timer
0,1,2,3 /
RTC
PCA/
WDT
SMBus
SPI
Port 2
Latch
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
XTAL1
XTAL2
External
Oscillator
Circuit
2%
Internal
Oscillator
System Clock
C
o
SFR Bus
r
e
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P3.0/C2D
Port 3
Latch
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CP1
Small Form Factor
Copyright 漏 2005 by Silicon Laboratories
9.14.2005
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