C8051F313
25 MIPS, 8 kB Flash, 10-Bit ADC, 28-Pin Mixed-Signal MCU
Analog Peripherals
10-Bit ADC
High-Speed 8051 碌C Core
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鹵1 LSB INL; no missing codes
Programmable throughput up to 200 ksps
Up to 17 external inputs; programmable as single-ended or differential
Data-dependent windowed interrupt generator
Built-in temperature sensor (鹵3 擄C)
Programmable hysteresis and response time
Configurable to generate interrupts or reset
Low current (0.4 碌A(chǔ))
Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
Up to 25 MIPS throughput with 25 MHz system clock
Expanded interrupt handler
1280 bytes internal data RAM (256 + 1 k)
8 kB Flash; in-system programmable in 512-byte sectors (512 bytes are
reserved)
25 port I/O; all are 5 V tolerant
Hardware SMBus鈩?(I2C鈩?compatible), SPI鈩? and UART serial ports
available concurrently
Programmable 16-bit counter/timer array with five capture/compare
modules, WDT
4 general-purpose 16-bit counter/timers
Realtime clock mode using timer or PCA
Internal oscillator: 24.5 MHz, 2% accuracy supports UART operation
External oscillator: Crystal, RC, C, or Clock (1 or 2 pin modes)
Can switch between clock sources on-the-fly
28-pin QFN (lead-free package)
C8051F313-GM
Memory
Two Comparators
Digital Peripherals
POR/Brown-out Detector
On-Chip Debug
On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
Provides breakpoints, single stepping
Inspect/modify memory and registers
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
Typical Operating Current: 7 mA at 25 MHz
15 碌A(chǔ) at 32 kHz
Typical Stop Mode Current: <0.1 碌A(chǔ)
Clock Sources
Supply Voltage: 2.7 to 3.6 V
Package
Ordering Part Number
Temperature Range: 鈥?0 to +85 擄C
VDD
Analog/Digital
Power
Port 0
Latch
Port 1
Latch
P
0
D
r
v
C
R
O
S
S
B
A
R
P
1
D
r
v
P
2
D
r
v
P
3
D
r
v
CP0
GND
UART
C2D
P0.0/VREF
P0.1
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVST
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0/C2D
Debug HW
Reset
RST/C2CK
POR
Brown-
Out
8
0
5
1
8 kB
FLASH
256 Byte
SRAM
1 kB
SRAM
Timer
0,1,2,3 /
RTC
PCA/
WDT
SMBus
SPI
Port 2
Latch
XTAL1
XTAL2
External
Oscillator
Circuit
2%
Internal
Oscillator
System Clock
C
o
SFR Bus
r
e
Port 3
Latch
+
-
+
-
Temp
CP1
VDD
VREF
10-bit
200 ksps
ADC
A
M
U
X
VDD/VREF
AIN0-AIN16
Small Form Factor
Copyright 漏 2005 by Silicon Laboratories
5.5.2005
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