C8051F231
25 MIPS, 8 kB Flash, 32-Pin Mixed-Signal MCU
Analog Peripherals
Two comparators
High-Speed 8051 碌C Core
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Programmable hysteresis
Configurable to generate interrupts or reset
V
DD
Monitor and Brown-out Detector
Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
Up to 25 MIPS throughput with 25 MHz system clock
Expanded interrupt handler; up to 21 interrupt sources
256 bytes data RAM
8 kB Flash; in-system programmable in 512 byte sectors (512 bytes are
reserved)
22 port I/O; all are 5 V tolerant
Hardware SPI鈩?and UART serial ports available concurrently
3 general-purpose 16-bit counter/timers
Dedicated watchdog timer; bidirectional reset
Internal programmable oscillator: 2鈥?6 MHz
External oscillator: Crystal, RC, C, or Clock
Can switch between clock sources on-the-fly
32-pin LQFP (standard lead and lead-free packages)
Lead-free package: C8051F231-GQ
Standard package: C8051F231
On-Chip JTAG Debug
Memory
On-chip emulation circuitry facilitates full-speed, non-intrusive, in-circuit
emulation
Supports breakpoints, single stepping, watchpoints, inspect/modify
memory, and registers
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
Fully compliant with IEEE 1149.1 specification
Typical operating current: 9 mA at 25 MHz
Typical stop mode current: <0.1 碌A(chǔ)
Digital Peripherals
Supply Voltage: 2.7 to 3.6 V
Temperature Range: 鈥?0 to +85 擄C
Clock Sources
Package
Part Ordering Numbers
VDD
GND
Analog/Digital
Power
Port 0
Latch
UART
Timer 0
Timer 1
Timer 2
P
0
M
U
X
P
0
D
r
v
P0.0/TX
P0.1/RX
P0.2//INT0
P0.3//INT1
P0.4/T0
P0.5/T1
P0.6/T2
P0.7/T2EX
TCK
TMS
TDI
TDO
RST
JTAG
Logic
Debug HW
Reset
8
0
5
1
C
o
r
e
8 kB FLASH
256 byte
RAM
Port 1
Latch
CP0
CP0+
CP0
P
1
M
U
X
P
1
D
r
v
CP0-
CP1+
CP1
CP1
P1.0/CP0+
P1.1/CP0-
P1.2/CP0
P1.3/CP1+
P1.4/CP1-
P1.5/CP1
P1.6/SYSCLK
P1.7
VDD
Monitor
External
Oscillator
Circuit
Internal
Oscillator
CP1-
SYSCLK
WDT
Port 2
Latch
SPI
XTAL1
XTAL2
SFR Bus
P
2
M
U
X
P
2
D
r
v
P
3
System Clock
P2.0/SCK
P2.1/MISO
P2.2/MOSI
P2.3/NSS
P2.4
P2.5
Port 3
Latch
D
r
v
NC
General Purpose
Copyright 漏 2005 by Silicon Laboratories
5.5.2005
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