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BU-65142 Datasheet

  • BU-65142

  • MIL-STD-1553 Components |Rad Hard simple system-To-1553

  • 28頁

  • ETC

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BU-65142 series*
MIL-STD-1553 DUAL REDUNDANT
REMOTE TERMINAL HYBRID
DESCRIPTION
The BU-65142 Series is a Hi-Rel
radiation tolerent complete dual
redundant MIL-STD-1553 Remote
Terminal Unit (RTU). The device is
based upon two DDC custom ICs,
which includes two monolithic bi-
polar low power transceivers and
one RiCmos protocol containing
data buffers and timing control logic.
It supports all 13 mode codes for dual
redundant operation, any combina-
tion of which can be illegalized.
Parallel data transfers are accom-
plished with a DMA type handshak-
ing, compatible with most CPU
types. Data transfers to/from mem-
ory are simplified by the latched
command word and word count out-
puts.
Error detection and recovery are
enhanced by BU-65142 Series spe-
cial features. A 14-bit built-in-test
word register stores RTU information,
and sends it to the Bus Controller in
response to the Mode Command
Transmit Bit Word. The BU-65142
Series performs continuous on-line
wraparound self-test, and provides
four error flags to the host CPU.
Inputs are provided for host CPU con-
trol of 6 bits of the RTU Status Word.
Its integrated hermetic package,
-55擄C to +125擄C operating tempera-
ture range, and complete RTU opera-
tion make the BU-65142 ideal for
MIL-STD-1553 applications requiring
hardware or microprocessor subsys-
tems.
FEATURES
鈥?/div>
Radiation Tolerant to 300 krad
鈥?/div>
Complete Integrated Remote
Terminal Including:
鈥揇ual Low-Power Transceivers
鈥揅omplete RT Protocol
鈥?/div>
Multiple Ordering Options;
+5V (Only), +5V/-15V, and +5V/-12V
鈥?/div>
Direct Interface to Systems With
No Processor
鈥?/div>
Space Qualified
鈥?/div>
High Reliability Screening
*
(Note:
BU-65142 is NOT recommended for new design, consult factory or local representative for more information)
DATA
BUS A
TRANSCEIVER
ENCODER/
DECODER
BIT
PROCESSOR
BUFFER
DB0-DB15
BUF ENA
DTREQ
DTGRT
DTACK
DTSTR
R/W
WATCHDOG
TIMEOUT
TRANSFER
CONTROLS
DATA
BUS B
TRANSCEIVER
ENCODER/
DECODER
BIT
PROCESSOR
CURRENT
WORD
COUNTER
PROTOCOL
SEQUENCER
AND
CONTROL
LOGIC
M
U
X
A0-A4
A5-A10
DAT/CMD
ILL CMD (ME)
SS REQ
ADBC
RT FLAG
SS BUSY
SS FLAG
MESS ERR
RT FAIL
HS FAIL
RTADD ERR
NBGT
INCMD
BITEN
STATEN
GBR
COMMAND
LATCH
RT ADDRESS
+
PARITY
STATUS
REGISTER
16 MHz CLOCK
ERROR FLAGS
TIMING FLAGS
DDC CUSTOM CHIP
D-RAD
FIGURE 1. BU-65142 SERIES BLOCK DIAGRAM
漏
1988, 1999 Data Device Corporation

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