BUS-61553
MIL-STD-1553 ADVANCED INTEGRATED
MUX (AIM ) HYBRID
ALSO
SEE
IDE
R鈥橲 GU
USE
DESCRIPTION
DDC鈥檚
BUS-61553
Advanced
Integrated Mux (AIM) Hybrid is a
complete
MIL-STD-1553
Bus
Controller (BC), Remote Terminal
Unit (RTU), and Bus Monitor (MT)
device. Packaged in a single 78-pin
DIP package, the BUS-61553 con-
tains dual low-power transceivers,
complete BC/RT/MT protocol logic, a
MIL-STD-1553-to-host interface unit
and 8K x 16 RAM.
Using an industry standard dual
transceiver and standard status and
control signals, the BUS-61553 sim-
plifies system integration at both the
MIL-STD-1553 and host processor
interface levels.
All 1553 operations are controlled
through the CPU access to the
shared 8K x 16 RAM. To ensure
maximum design flexibility, memory
control lines are provided for attach-
ing external RAM to the BUS-61553
address and data buses and for dis-
abling internal memory; the total
combined memory space can be
expanded to 64K x 16. All 1553 trans-
fers are entirely memory-mapped;
thus the CPU interface requires
minimal hardware and/or software
support.
The BUS-61553 operates over the
full military -55擄C to +125擄C temper-
ature range. Available screened to
MIL-PRF-38534, the BUS-61553 is
ideal for demanding military and
industrial microprocessor-to-1553
interface applications.
FEATURES
鈥?Fully Intergrated Terminal
Including:
鈥揇ual Transceiver
鈥揃C/RT/MT Protocol
鈥揗emory Management Unit
鈥揚(yáng)rocessor lnterface Logic
鈥?K x 16 RAM
鈥?CMOS and Bipolar Technologies
鈥?Internal Interrupt Status and Time
Tag Registers
鈥?High Reliability
鈥?883B Processing Available
BUS-25679
8
1
DATA
BUS A
2
4
3
TRANSCEIVER A
TX INH
TX
RX
RX
CONTENTION
RESOLVER
INTERRUPT
GENERATOR
CLOCK IN
CHANNEL A
ENCODER/
DECODER
MEMORY
TIMING
CPU
TIMING
MSTRCLR
SELECT
STRBD
READYD
RD/WR
MEM/REG
EXTEN
EXTLD
INT
TRANSFORMER A
768
碌s
TIME OUT
PROTOCOL
CONTROLLER
A15-A00
BUS-25679
8
DATA
BUS B
4
1
2
3
TX INH
TX
RX
RX
TRANSCEIVER B
D15-D00
TRANSFORMER B
CHANNEL B
ENCODER/
DECODER
8K x 16
SHARED RAM
PARITY
CHECKER
RT ADDR
RTAD0
RTAD1
RTAD2
RTAD3
RTAD4
RTAD P
RTPARERR
RAM
FIGURE 1. BU-61553 BLOCK DIAGRAM
漏 1987, 1999 Data Device Corporation
1
2
3
4
