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BUS-61559-120L Datasheet

  • BUS-61559-120L

  • MIL-STD-1553B NOTICE 2 ADVANCED INTEGRATED MUX HYBRIDS WITH ...

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BUS-61559 SERIES
MIL-STD-1553B NOTICE 2
ADVANCED INTEGRATED MUX HYBRIDS
WITH ENHANCED RT FEATURES (AIM-HY鈥檈r)
DESCRIPTION
DDC鈥檚 BUS-61559 series of Advanced
Integrated Mux Hybrids with enhanced
RT Features (AIM-HY鈥檈r) comprise a
complete interface between a micro-
processor and a MIL-STD-1553B
Notice 2 bus, implementing Bus
Controller (BC), Remote Terminal (RX,
and Monitor Terminal (MT) modes.
Packaged in a single 78-pin DIP or
82-pin flat package the BUS-61559
series contains dual low-power trans-
ceivers and encoder/decoders, com-
plete BC/RT/MT protocol logic, memory
management and interrupt logic, 8K x 16
of shared static RAM, and a direct,
buffered interface to a host processor bus.
buffers to provide a direct interface to
a host processor bus. Alternatively,
the buffers may be operated in a fully
transparent mode in order to interface
to up to 64K words of external shared
RAM and/or connect directly to a com-
ponent set supporting the 20 MHz
STANAG-3910 bus.
The memory management scheme
for RT mode prevails an option for
separation of broadcast data, in com-
pliance with 1553B Notice 2. A circu-
lar buffer option for RT message data
blocks offloads the host processor for
bulk data transfer applications.
FEATURES
鈥?/div>
Complete Integrated 1553B
Notice 2 Interface Terminal
鈥?/div>
Functlonal Superset of BUS-
61553 AlM-HYSeries
鈥?/div>
Internal Address and Data
Buffers for Dlrect Interface to
Processor Bus
鈥?/div>
RT Subaddress Circular Buffers
to Support Bulk Data Transfers
Another feature besides those listed
The BUS-61559 includes a number of
to the right, is a transmitter inhibit con-
advanced features in support of
trol for the individual bus channels.
MIL-STD-1553B Notice 2 and STANAG
3838. Other salient features of the The BUS-61559 series hybrids oper-
BUS-61559 serve to provide the bene- ate over the full military temperature
fits of reduced board space require- range of -55 to +125鈥滳 and MIL-PRF-
ments enhanced software flexibility, 38534 processing is available. The
and reduced host processor overhead hybrids are ideal for demanding mili-
tary and industrial microprocessor-to-
The BUS-61559 contains internal
1553 applications
address latches and bidirectional data
鈥?/div>
Optlonal Separatlon of
RT Broadcast Data
鈥?/div>
Internal Interrupt Status and
Time Tag Registers
鈥?/div>
Internal ST Command
Illegalization
鈥?/div>
MIL-PRF-38534 Processing
Available
(ILLEGALIZATION ILLENA
ENABLE)
ILLEGALLIZATION
LOGIC
8K x 16
DUAL
PORT
RAM
BUS-25679
8
1
7
2
5
4
3
TX_INH_A
CLK IN (16MHz)
LOW-POWER
TRANSCEIVER
A
DUAL
ENCODER/
DECODER
BC/RT/MT
PROTOCOL
LOW-POWER
TRANSCEIVER
A
MEMORY DATA
DATA
BUFFERS*
D15-D鈭?/div>
(PROCESSOR
DATA)
BUS-25679
8
1
7
2
5
4
3
TX_INH_A
(RT ADDRESS)
(BROADCAST
ENABLE)
(RTFAIL,
RTFLAG)
(BROADCAST,
MESSAGE
TIMING, DATA
STROBE AND ERROR
INDICATORS)
MEMORY ADDRESS
ADDRESS
LATCHES/
BUFFERS*
A15-A鈭?/div>
(PROCESSOR
ADDRESS)
LATCH
CONTROL)
ADDR_LAT
(ADDRESS
RTAD 4-鈭? RTADP
BRO_ENA
RTFAIL
RTFLAG
BCSTRCV, CMD_STR, TXDTA_STR
RXDTA_STR, MSG_ERR, INCMD
TRANSPARENT/BUFFERED, MSTCLR,
STRBD, SELECT, MEM/REG, RD/WR
MEMORY
IOEN, READYD
MANAGEMENT,
INT
SHARED
MEMEN-OUT,MEMWR, MEMOE
RAM/
PROCESSOR
MEMENA-IN
INTERFACE,
SSFLAG
INTERRUPT
LOGIC
TAGCLK
(PROCESSOR
CONTROL)
(INTERRUPT
REQUEST)
(MEMORY
CONTROL)
(SUBSYSTEM
FLAG)
(TIME TAG
CLOCK)
BU-61559 BLOCK DIAGRAM
漏 1990, 1999 Data Device Corporation

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