BU-65142 and BUS-65142 SERIES
MIL-STD-1553 DUAL REDUNDANT
REMOTE TERMINAL HYBRID
DESCRIPTION
The BUS-65142 Series is a com-
plete dual redundant MIL-STD-
1553 Remote Terminal Unit (RTU)
packaged in a small 1.9" x 2.1"
hybrid. The device is based upon
two DDC custom ICs, which
includes two monolithic bi-polar low
power transceivers and one CMOS
protocol containing data buffers
and timing control logic. It supports
all 13 mode codes for dual redun-
dant operation, any combinaion of
which can be illegalized.
Parallel data transfers are accom-
plished with a DMA type handshak-
ing, compatible with most CPU
types. Data transfers to/from mem-
ory are simplified by the latched
command word and word count out-
puts.
Error detection and recovery are
enhanced by BUS-65142 Series
special features. A 14-bit built-in-
test word register stores RTU infor-
mation, and sends it to the Bus
Controller in response to the Mode
Command Transmit Bit Word. The
BUS-65142 Series performs contin-
uous on-line wraparound self-test,
and provides four error flags to the
host CPU. Inputs are provided for
host CPU control of 6 bits of the
RTU Status Word.
Its small hermetic package, -55擄C
to +125擄C operating temperature
range, and complete RTU operation
make the BUS-65142 ideal for most
MIL-STD-1553 applications requir-
ing hardware or microprocessor
subsystems.
FEATURES
鈥?/div>
Complete Intergrated Remote
Terminal Including:
鈥揇ual Low-Power Transceivers
鈥揅omplete RT Protocol
鈥?/div>
Direct Interface to Systems With
No Processor
鈥?/div>
Radiation Tolerant Version
Available
鈥?/div>
Space Qualified Version
Available
鈥?/div>
High Reliability Screening
Available
DATA
BUS A
TRANSCEIVER
ENCODER/
DECODER
BIT
PROCESSOR
BUFFER
DB0-DB15
BUF ENA
DTREQ
DTGRT
DTACK
DTSTR
R/W
WATCHDOG
TIMEOUT
TRANSFER
CONTROLS
DATA
BUS B
TRANSCEIVER
ENCODER/
DECODER
BIT
PROCESSOR
CURRENT
WORD
COUNTER
PROTOCOL
SEQUENCER
AND
CONTROL
LOGIC
M
U
X
A0-A4
A5-A10
DAT/CMD
ILL CMD (ME)
SS REQ
ADBC
RT FLAG
SS BUSY
SS FLAG
MESS ERR
RT FAIL
HS FAIL
RTADD ERR
NBGT
INCMD
BITEN
STATEN
GBR
COMMAND
LATCH
RT ADDRESS
PARITY
STATUS
REGISTER
16 MHz CLOCK
ERROR FLAGS
TIMING FLAGS
DDC CUSTOM CHIP
FIGURE 1. BUS-65142 SERIES BLOCK DIAGRAM
漏
1988, 1999 Data Device Corporation
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