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BU-61845F3-110 Datasheet

  • BU-61845F3-110

  • Telecommunication IC

  • 56頁

  • ETC

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BU-6174X/6184X/6186X
ENHANCED MINIATURE ADVANCED
COMMUNICATIONS ENGINE
(ENHANCED MINI-ACE)
FEATURES
DESCRIPTION
The Enhanced Mini-ACE family of
MIL-STD-1553 terminals provide
complete interfaces between a host
processor and a 1553 bus. These
terminals integrate dual transceiver,
protocol logic, and 4K words or 64K
words of RAM.
With a 1.0 inch square package, the
Enhanced Mini-ACE is nearly 100%
footprint and software compatibile
with the previous generation Mini-
ACE (Plus) terminals, and is soft-
ware compatibile with the older ACE
series.
The Enhanced Mini-ACE is powered
by a choice 5V, or 5V/3.3V (3.3V
logic). Multiprotocol support of
MIL-STD-1553A/B and STANAG
3838, including versions incorporat-
ing McAir compatible transmitters, is
provided. There is a choice of 10, 12,
16, or 20 Mhz clocks. The BC/RT/MT
versions with 64K words of RAM
include built-in RAM parity checking.
BC features include a built-in mes-
sage sequence control engine, with
a set of 20 instructions. This provides
an autonomous means of imple-
menting
multi-frame
message
scheduling, message retry schemes,
data double buffering, asynchronous
message insertion, and reporting to
the host CPU. The Enhanced
Mini-ACE incorporates a fully
autonomous built-in self-test, which
provides comprehensive testing of
the internal protocol logic and/or
RAM.
The Enhanced Mini-ACE RT offers
the same choices of subaddress
buffering as the ACE and Mini-ACE
(Plus), along with a global circular
buffering option, 50% rollover inter-
rupt for circular buffers, an interrupt
status queue, and an "Auto-boot"
option to support MIL-STD-1760.
The Enhanced Mini-ACE terminals
provide the same flexibility in host
interface configurations as the
ACE/Mini-ACE, along with a reduc-
tion in the host processor's worst
case holdoff time.
鈥?/div>
FULLY INTEGRATED 1553A/B NOTICE 2,
鈥?/div>
COMPATIBLE WITH MINI-ACE (PLUS)
AND ACE GENERATIONS
MCAIR, STANAG 3838 INTERFACE TERMINAL
鈥?/div>
CHOICE OF :
鈥?/div>
RT OR BC/RT/MT IN SAME FOOTPRINT
鈥?/div>
RT OR BC/RT/MT WITH 4K RAM
鈥?/div>
BC/RT/MT WITH 64K RAM, WITH RAM PARITY
鈥?/div>
CHOICE OF 5V OR 3.3V LOGIC
鈥?/div>
5V TRANSCEIVER WITH 1760 AND
MCAIR COMPATIBLE OPTIONS
鈥?/div>
COMPREHENSIVE BUILT-IN SELF-TEST
鈥?/div>
FLEXIBLE PROCESSOR/MEMORY
INTERFACE, WITH REDUCED HOST WAIT TIME
鈥?/div>
CHOICE OF 10, 12, 16, OR 20 MHZ CLOCK
鈥?/div>
HIGHLY AUTONOMOUS BC WITH
BUILT-IN MESSAGE SEQUENCE CONTROL:
鈥?/div>
FRAME SCHEDULING
鈥?/div>
BRANCHING
鈥?/div>
ASYNCHRONOUS MESSAGE INSERTION
鈥?/div>
GENEERAL PURPOSE QUEUE
鈥?/div>
USER-DEFINED INTERRUPTS
鈥?/div>
ADVANCED RT FUNCTIONS
INTERRPTS
鈥?/div>
GLOBAL CIRCULAR BUFFERING
鈥?/div>
INTERRUPT STATUS QUEUE
鈥?/div>
50% CIRCULAR BUFFER ROLLOVER
TX/RX_A
SHARED
RAM
CH. A
TRANSCEIVER
A
DATA
BUFFERS
PROCESSOR
DATA BUS
*
TX/RX_A
DATA BUS
DUAL
ENCODER/DECODER,
MULTIPROTOCOL
AND
MEMORY
MANAGEMENT
D15-D0
TX/RX_B
ADDRESS BUS
ADDRESS
BUFFERS
A15-A0
PROCESSOR
ADDRESS BUS
CH. B
TRANSCEIVER
B
TX/RX_B
PROCESSOR
AND
MEMORY
INTERFACE
LOGIC
TRANSPARENT/BUFFERED, STRBD, SELECT,
RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,
MSB/LSB/DTGRT
IOEN, READYD
ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,
8/16-BIT/DTREQ, POLARITY_SEL/DTACK
INT
PROCESSOR
AND
MEMORY
CONTROL
INTERRUPT
REQUEST
RT ADDRESS
RTAD4-RTAD0, RTADP
INCMD
MISCELLANEOUS
CLK_IN, TAG_CLK,
MSTCLR,SSFLAG/EXT_TRG
* SEE ORDERING INFORMATION FOR AVAILABLE MEMORY
FIGURE 1. ENHANCED MINI-ACE BLOCK DIAGRAM
漏
2000 Data Device Corporation

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