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BU-61585 Datasheet

  • BU-61585

  • MIL-STD-1553 Components |ACE

  • 44頁(yè)

  • ETC

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BU-65170/61580 and BU-61585
MIL-STD-1553A/B NOTICE 2 RT and BC/RT/MT,
ADVANCED COMMUNICATION ENGINE (ACE)
ACE User鈥檚 Guide
Also Available
DESCRIPTION
DDC's BU-65170, BU-61580 and
BU-61585 Bus Controller / Remote
Terminal
/
Monitor
Terminal
(BC/RT/MT)
A d v a n c e d
Communication Engine (ACE) termi-
nals comprise a complete integrated
interface between a host processor
and a MIL-STD-1553 A and B or
STANAG 3838 bus.
The ACE series is packaged in a 1.9 -
square-inch, 70-pin, low-profile,
cofired MultiChip Module (MCM)
ceramic package that is well suited for
applications with stringent height
requirements.
The BU-61585 ACE integrates dual
transceiver, protocol, memory man-
agement, processor interface logic,
and a total of 12K words of RAM in a
choice of DIP or flat pack packages.
The BU-61585 requires +5 V power
and either -15 V or -12 V power.
The BU-61585 internal RAM can be
configured as 12K x 16 or 8K x 17.
The 8K x 17 RAM feature provides
capability for memory integrity check-
ing by implementing RAM parity gen-
eration and verification on all access-
es. To minimize board space and
鈥済lue鈥?logic, the ACE provides ultimate
flexibility in interfacing to a host
processor and internal/external RAM.
The advanced functional architecture
of the ACE terminals provides soft-
ware
compatibility
to
DDC's
Advanced Integrated Multiplexer (AIM)
series hybrids, while incorporating a
multiplicity of architectural enhance-
ments. It allows flexible operation
while off-loading the host processor,
ensuring data sample consistency,
and supports bulk data transfers.
The ACE hybrids may be operated at
either 12 or 16 MHz. Wire bond
options allow for programmable RT
address (hardwired is standard) and
external transmitter inhibit inputs.
FEATURES
鈥?/div>
Fully Integrated MIL-STD-1553
Interface Terminal
Interface
鈥?/div>
Flexible Processor/Memory
鈥?/div>
Standard 4K x 16 RAM and
鈥?/div>
Optional RAM Parity
Optional 12K x 16 or 8K x 17 RAM
Available
Generation/Checking
鈥?/div>
Automatic BC Retries
鈥?/div>
Programmable BC Gap Times
鈥?/div>
BC Frame Auto-Repeat
鈥?/div>
Flexible RT Data Buffering
鈥?/div>
Programmable Illegalization
鈥?/div>
Selective Message Monitor
鈥?/div>
Simultaneous RT/Monitor Mode
TX/RX_A
SHARED
RAM
CH. A
TRANSCEIVER
A
DATA
BUFFERS
PROCESSOR
DATA BUS
*
TX/RX_A
DATA BUS
DUAL
ENCODER/DECODER,
MULTIPROTOCOL
AND
MEMORY
MANAGEMENT
D15-D0
TX/RX_B
ADDRESS BUS
ADDRESS
BUFFERS
A15-A0
PROCESSOR
ADDRESS BUS
CH. B
TRANSCEIVER
B
TX/RX_B
PROCESSOR
AND
MEMORY
INTERFACE
LOGIC
TRANSPARENT/BUFFERED, STRBD, SELECT,
RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,
MSB/LSB/DTGRT
IOEN, MEMENA-OUT, READYD
ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,
8/16-BIT/DTREQ, POLARITY_SEL/DTACK
INT
PROCESSOR
AND
MEMORY
CONTROL
INTERRUPT
REQUEST
RT ADDRESS
RTAD4-RTAD0, RTADP
INCMD
MISCELLANEOUS
CLK_IN, TAG_CLK,
MSTCLR,SSFLAG/EXT_TRG
* SEE ORDERING INFORMATION FOR AVAILABLE MEMORY
FIGURE 1. ACE BLOCK DIAGRAM
漏
1992, 1999 Data Device Corporation

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