BSI
FEATURES
Very Low Power/Voltage CMOS SRAM
256K X 8 bit
DESCRIPTION
BS62LV2009
鈥?Vcc operation voltage : 2.4V ~ 3.6V
鈥?Very low power consumption :
Vcc = 3.0V C-grade: 22mA (@55ns) operating current
I -grade: 23mA (@55ns) operating current
C-grade: 17mA (@70ns) operating current
I -grade: 18mA (@70ns) operating current
0.3uA(Typ.) CMOS standby current
鈥?High speed access time :
-55
55ns
-70
70ns
鈥?Automatic power down when chip is deselected
鈥?Three state outputs and TTL compatible
鈥?Fully static operation
鈥?Data retention supply voltage as low as 1.5V
鈥?Easy expansion with CE2, CE1, and OE options
The BS62LV2009 is a high performance, very low power CMOS
Static Random Access Memory organized as 262,144 words by 8 bits
and operates from a range of 2.4V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.3u
A
at 3.0
V
/25
o
C
and maximum access time of 55ns at 3.0
V
/ 85
o
C
.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
The BS62LV2009 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV2009 is available in DICE form, JEDEC standard 32 pin
450mil Plastic SOP, 8mmx13.4mm STSOP and 8mmx20mm TSOP.
PRODUCT FAMILY
PRODUCT
FAMILY
BS62LV2009DC
BS62LV2009TC
BS62LV2009STC
BS62LV2009SC
BS62LV2009DI
BS62LV2009TI
BS62LV2009STI
BS62LV2016SI
OPERATING
TEMPERATURE
Vcc
RANGE
SPEED
( ns )
55ns: 3.0~3.6V
70ns: 2.7~3.6V
( I
CCSB1
, Max )
Vcc=3.0V
POWER DISSIPATION
STANDBY
Operating
( I
CC
, Max )
Vcc=3.0V
55ns
70ns
PKG TYPE
DICE
TSOP-32
STSOP-32
SOP-32
DICE
TSOP-32
STSOP-32
SOP-32
+0 C to +70 C
O
O
2.4V ~3.6V
55/70
3uA
22mA
17mA
-40
O
C to +85
O
C
2.4V ~ 3.6V
55/70
5uA
23mA
18mA
PIN CONFIGURATIONS
BLOCK DIAGRAM
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
A13
A17
A15
A16
A14
A12
A7
A6
A5
A4
鈥?/div>
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
BS62LV2009TC
BS62LV2009STC
BS62LV2009TI
BS62LV2009STI
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
BS62LV2009SC
8
BS62LV2009SI
9
10
11
12
13
14
15
16
A11
A9
A8
A13
WE
CE2
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
Address
Input
Buffer
20
Row
Decoder
1024
Memory Array
1024 x 2048
2048
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Input
Buffer
8
Column I/O
Write Driver
Sense Amp
256
Column Decoder
16
Control
Address Input Buffer
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
Brilliance Semiconductor, Inc
.
reserves the right to modify document contents without notice.
R0201-BS62LV2009
鈥?/div>
8
Data
Output
Buffer
8
CE1
CE2
WE
OE
Vdd
Gnd
A11 A9 A8 A3 A2 A1 A0 A10
1
Revision 1.1
Jan.
2004
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