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BS616UV8021FI Datasheet

  • BS616UV8021FI

  • Ultra Low Power/Voltage CMOS SRAM 512K x 16 or 1M x 8 bit sw...

  • 12頁

  • BSI

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BSI
FEATURES
Ultra Low Power/Voltage CMOS SRAM
512K x 16 or 1M x 8 bit switchable
DESCRIPTION
BS616UV8021
鈥?Ultra low operation voltage : 1.8 ~ 2.3V
鈥?Ultra low power consumption :
Vcc = 2.0V C-grade: 20mA (Max.) operating current
I-grade : 25mA (Max.) operating current
0.6uA (Typ.) CMOS standby current
鈥?High speed access time :
-70
70ns (Max.) at Vcc=2.0V
-10 100ns (Max.) at Vcc=2.0V
鈥?Automatic power down when chip is deselected
鈥?Three state outputs and TTL compatible
鈥?Fully static operation
鈥?Data retention supply voltage as low as 1.5V
鈥?Easy expansion with CE1, CE2 and OE options
鈥?I/O Configuration x8/x16 selectable by CIO, LB and UB pin
The BS616UV8021 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 524,288 words by 16 bits or
1,048,576 bytes by 8 bits selectable by CIO pin and operates from a wide
range of 1.8V to 2.3V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.6uA and maximum access time of 70/100ns in 2.0V operation.
Easy memory expansion is provided by an active HIGH chip
enable2(CE2), active LOW chip enable1(CE1), active LOW output
enable(OE) and three-state output drivers.
The BS616UV8021 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616UV8021 is available in DICE form and 48-pin BGA type.
PRODUCT FAMILY
PRODUCT
FAMILY
BS616UV8021DC
BS616UV8021BC
BS616UV8021FC
BS616UV8021DI
BS616UV8021BI
BS616UV8021FI
OPERATING
TEMPERATURE
SPEED
(ns)
Vcc=2.0V
Vcc RANGE
POWER DISSIPATION
STANDBY
Operating
(I
CCSB1
, Max)
(I
CC
, Max)
PKG TYPE
Vcc=2.0V
Vcc=2.0V
+0 C to +70 C
O
O
O
O
1.8V ~ 2.3V
70 / 100
15uA
20mA
-40 C to +85 C
1.8V ~ 2.3V
70 / 100
20uA
25mA
DICE
BGA-48-0810
BGA-48-0912
DICE
BGA-48-0810
BGA-48-0912
PIN CONFIGURATIONS
1
A
B
C
D
E
F
G
H
LB
D8
D9
VSS
VCC
D14
D15
A18
2
OE
UB
D10
D11
D12
D13
CIO
.
A8
3
A0
A3
A5
A17
Vss
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CE1
D1
D3
D4
D5
6
CE2
D0
D2
VCC
VSS
D6
BLOCK DIAGRAM
A15
A14
A13
A12
A11
A10
A9
A8
A17
A7
A6
Address
Input
Buffer
22
Row
Decoder
2048
Memory Array
2048 x 4096
4096
D0
16(8)
Data
Input
Buffer
16(8)
Column I/O
.
.
.
.
D15
CE1
CE2
WE
OE
UB
LB
CIO
Vdd
Vss
.
.
.
.
Write Driver
16(8)
Sense Amp
256(512)
Column Decoder
16(8)
Data
Output
Buffer
16(18)
Control
Address Input Buffer
WE
A11
D7
SAE
.
A16 A0 A1 A2 A3 A4 A5 A18 (SAE)
48-Ball CSP top View
Brilliance Semiconductor Inc
.
reserves the right to modify document contents without notice.
R0201-BS616UV8021
1
Revision 2.2
April 2001

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