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BSI

FEATURES

Ultra Low Power/Voltage CMOS SRAM

512K X 16 bit

DESCRIPTION

BS616UV8010

鈥?Ultra low operation voltage : 1.8 ~ 3.6V

鈥?Ultra low power consumption :

Vcc = 2.0V C-grade: 15mA (Max.) operating current

I-grade : 20mA (Max.) operating current

0.4uA (Typ.) CMOS standby current

Vcc = 3.0V C-grade: 20mA (Max.) operating current

I-grade : 25mA (Max.) operating current

0.5uA (Typ.) CMOS standby current

鈥?High speed access time :

-70

70ns (Max.) at Vcc=2V

-10

100ns (Max.) at Vcc=2V

鈥?Automatic power down when chip is deselected

鈥?Three state outputs and TTL compatible

鈥?Fully static operation

鈥?Data retention supply voltage as low as 1.5V

鈥?Easy expansion with CE2,CE1 and OE options

鈥?I/O Configuration x8/x16 selectable by LB and UB pin

The BS616UV8010 is a high performance, ultra low power CMOS Static

Random Access Memory organized as 524,288 words by 16 bits and

operates from a wide range of 1.8V to 3.6V supply voltage.

Advanced CMOS technology and circuit techniques provide both high

speed and low power features with a typical CMOS standby current

of 0.4uA and maximum access time of 70/100ns in 2V operation.

Easy memory expansion is provided by an active LOW chip enable(CE1),

active HIGH chip enable (CE2), active LOW output enable(OE) and

three-state output drivers.

The BS616UV8010 has an automatic power down feature, reducing the

power consumption significantly when chip is deselected.

The BS616UV8010 is available in 48-pin BGA package.

PRODUCT FAMILY

SPEED

PRODUCT FAMILY

OPERATING

TEMPERATURE

Vcc

RANGE

POWER DISSIPATION

STANDBY

(I

CCSB1

, Max)

Operating

(I

CC

, Max)

PKG TYPE

(ns)

Vcc=2 V Vcc=2V Vcc=3V Vcc=2V Vcc=3V

BS616UV8010BC

BS616UV8010BI

+0 C to +70 C 1.8V ~ 3.6V 70 / 100

O

O

-

40 C to +85 C 1.8V ~ 3.6V 70 / 100

O

O

2uA

4uA

3uA

6uA

15mA

20mA

20mA

25mA

BGA

-

48

-

0810

BGA

-

48

-

0810

PIN CONFIGURATIONS

1

A

B

C

D

E

F

G

H

LB

D8

D9

VSS

VCC

D14

D15

A 18

2

OE

UB

D10

D11

D12

D13

NC

.

A8

3

A0

A3

A5

A17

VSS

A14

A 12

A9

4

A1

A4

A6

A7

A16

A15

A13

A10

5

A2

CE1

D1

D3

D4

D5

WE

A11

6

CE2

D0

D2

VCC

VSS

D6

D7

BLOCK DIAGRAM

A4

A3

A2

A1

A0

A17

A16

A15

A14

A13

A12

Address

Input

Buffer

22

Row

Decoder

2048

Memory Array

2048 x 4096

4096

D0

16

Data

Input

Buffer

16

Column I/O

.

.

.

.

D15

CE2

CE1

WE

OE

UB

LB

.

.

.

.

Write Driver

Sense Amp

256

Column Decoder

16

Data

Output

16

Buffer

16

Control

Address Input Buffer

NC

A11 A10 A9 A8 A7 A6 A5 A18

Vcc

Gnd

48-Ball CSP top View

Brilliance Semiconductor Inc

. reserves the right to modify document contents without notice.

R0201-BS616UV8010

1

Revision 2.4

April 2002

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