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BSI

FEATURES

Ultra Low Power/Voltage CMOS SRAM

256K x 16 or 512K x 8 bit switchable

DESCRIPTION

BS616UV4020

鈥?Ultra low operation voltage : 1.8 ~ 3.6V

鈥?Ultra low power consumption :

Vcc = 2.0V C-grade: 15mA (Max.) operating current

I-grade : 20mA (Max.) operating current

0.2uA (Typ.) CMOS standby current

Vcc = 3.0V C-grade: 20mA (Max.) operating current

I-grade : 25mA (Max.) operating current

0.25uA (Typ.) CMOS standby current

鈥?High speed access time :

-70

70ns (Max.) at Vcc=2.0V

-10

100ns (Max.) at Vcc=2.0V

鈥utomatic power down when chip is deselected

鈥?Three state outputs and TTL compatible

鈥?Fully static operation

鈥?Data retention supply voltage as low as 1.5V

鈥?Easy expansion with CE1, CE2 and OE options

鈥?I/O Configuration x8/x16 selectable by CIO, LB and UB pin

The BS616UV4020 is a high performance, ultra low power CMOS Static

Random Access Memory organized as 262,144 words by 16 bits or

524,288 bytes by 8 bits selectable by CIO pin and operates from a

wide range of 1.8V to 3.6V supply voltage.

Advanced CMOS technology and circuit techniques provide both high

speed and low power features with a typical CMOS standby current

of 0.2uA and maximum access time of 70/100ns in 2V operation.

Easy memory expansion is provided by active HIGH chip

enable2(CE2), active LOW chip enable1(CE1), active LOW

output enable(OE) and three-state output drivers.

The BS616UV4020 has an automatic power down feature, reducing the

power consumption significantly when chip is deselected.

The BS616UV4020 is available in DICE form and 48-pin BGA type.

PRODUCT FAMILY

PRODUCT FAMILY

BS616UV4020DC

BS616UV4020BC

BS616UV4020DI

BS616UV4020BI

OPERATING

TEMPERATURE

O

O

Vcc RANGE

SPEED

(ns)

Vcc=2V

POWER DISSIPATION

STANDBY

Operating

(I

CCSB1

, Max)

(I

CC

, Max)

PKG TYPE

DICE

BGA-48-0810

DICE

BGA-48-0810

Vcc=2V

Vcc=3V

Vcc=2V

Vcc=3V

Vcc=3V

+0 C to +70 C

-40 C to +85 C

O

O

1.8V ~ 3.6V

1.8V ~ 3.6V

70 / 100

70 / 100

1uA

2uA

1.5uA

3uA

15mA

20mA

20mA

25mA

PIN CONFIGURATION

BLOCK DIAGRAM

A15

A14

A13

A12

A11

A10

A9

A8

A17

A7

A6

Address

Input

Buffer

22

Row

Decoder

2048

Memory Array

2048 x 2048

2048

D0

16(8)

Data

Input

Buffer

16(8)

Column I/O

.

.

.

.

D15

CE1

CE2

WE

OE

UB

LB

CIO

Vdd

Vss

.

.

.

.

Write Driver

16(8)

Sense Amp

128(256)

Column Decoder

16(8)

Data

Output

Buffer

14(16)

Control

Address Input Buffer

A16 A0 A1 A2 A3 A4 A5

(SAE)

Brilliance Semiconductor Inc

. reserves the right to modify document contents without notice.

R0201-BS616UV4020

1

Revision 2.4

April 2002

next

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