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BSI

FEATURES

Ultra Low Power/Voltage CMOS SRAM

1M x 16 or 2M x 8 bit switchable

DESCRIPTION

BS616UV1620

鈥?Ultra low operation voltage : 1.8 ~ 2.3V

鈥?Ultra low power consumption :

Vcc = 1.8V C-grade : 25mA (Max.) operating current

I- grade : 30mA (Max.) operating current

1.2uA (Typ.) CMOS standby current

鈥?High speed access time :

-70

70ns (Max.) at Vcc = 2.0V

-10 100ns (Max.) at Vcc = 2.0V

鈥?Automatic power down when chip is deselected

鈥?Three state outputs and TTL compatible

鈥?Fully static operation

鈥?Data retention supply voltage as low as 1.5V

鈥?Easy expansion with CE1, CE2 and OE options

鈥?I/O Configuration x8/x16 selectable by CIO, LB and UB pin

The BS616UV1620 is a high performance, ultra low power CMOS Static

Random Access Memory organized as 1,048,676 words by 16 bits or

2,097,152 bytes by 8 bits selectable by CIO pin and operates in a wide

range of 1.8V to 2.3V supply voltage.

Advanced CMOS technology and circuit techniques provide both high

speed and low power features with a typical CMOS standby current

of 1.2uA and maximum access time of 70/100ns in 2.0V operation.

This device provide three control inputs and three states output drivers

for easy memory expansion.

The BS616UV1620 has an automatic power down feature, reducing the

power consumption significantly when chip is deselected.

The BS616UV1620 is available in DICE form and 48-pin BGA type.

PRODUCT FAMILY

SPEED

(ns)

Vcc=2.0V

PRODUCT

FAMILY

BS616UV1620BC

BS616UV1620FC

BS616UV1620BI

BS616UV1620FI

OPERATING

TEMPERATURE

+0

O

C to +70

O

C

-40

O

C to +85

O

C

Vcc RANGE

POWER DISSIPATION

STANDBY

Operating

(I

CCSB1

, Max)

(I

CC

, Max)

PKG TYPE

BGA-48-0810

BGA-48-0912

BGA-48-0810

BGA-48-0912

Vcc=2.0V

Vcc=2.0V

1.8V ~ 2.3V

1.8V ~ 2.3V

70 / 100

70 / 100

30uA

40uA

25mA

30mA

PIN CONFIGURATIONS

1

A

B

C

D

E

F

G

H

LB

D8

D9

VSS

VCC

D14

D15

A18

2

OE

UB

D10

D11

D12

D13

CIO

.

A8

3

A0

A3

A5

A17

A19

A14

A12

A9

4

A1

A4

A6

A7

A16

A15

A13

A10

5

A2

CE1

D1

D3

D4

D5

WE

A11

6

CE2

D0

D2

BLOCK DIAGRAM

A19

A15

A14

A13

A12

A11

A10

A9

A8

A17

A7

A6

Address

Input

Buffer

24

Row

Decoder

4096

Memory Array

4096 x 4096

4096

D0

16(8)

Data

Input

Buffer

16(8)

Column I/O

VCC

VSS

D6

D7

SAE

.

.

.

.

.

D15

CE1

CE2

WE

OE

UB

LB

CIO

Vdd

Vss

.

.

.

.

Write Driver

16(8)

Sense Amp

256(512)

Column Decoder

16(8)

Data

Output

Buffer

16(18)

Control

Address Input Buffer

A16 A0 A1 A2 A3 A4 A5 A18 (SAE)

48-Ball CSP top View

Brilliance Semiconductor Inc

. reserves the right to modify document contents without notice.

R0201-BS616UV1620

1

Revision 2.2

April 2001

next

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