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BS616LV2025DI Datasheet

  • BS616LV2025DI

  • Very Low Power/Voltage CMOS SRAM 128K x 16 or 256K x 8 bit s...

  • 11頁

  • BSI

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BSI
FEATURES
Very Low Power/Voltage CMOS SRAM
128K x 16 or 256K x 8 bit switchable
DESCRIPTION
BS616LV2025
鈥?Very low operation voltage : 4.5 ~ 5.5V
鈥?Very low power consumption :
Vcc = 5.0V
C-grade: 40mA (Max.) operating current
I -grade: 45mA (Max.) operating current
0.6uA (Typ.) CMOS standby current
鈥?High speed access time :
-70
70ns (Max.) at Vcc = 5.0V
-55
55ns (Max.) at Vcc = 5.0V
鈥?Automatic power down when chip is deselected
鈥?Three state outputs and TTL compatible
鈥?Fully static operation
鈥?Data retention supply voltage as low as 1.5V
鈥?Easy expansion with CE1, CE2 and OE options
鈥?I/O Configuration x8/x16 selectable by CIO, LB and UB pin
The BS616LV2025 is a high performance, very low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits or
262,144 bytes by 8 bits selectable by CIO pin and operates from a wide
range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.6uA and maximum access time of 70/55 ns in 5V operation.
Easy memory expansion is provided by active HIGH chip
enable2(CE2), active LOW chip enable1(CE1), active LOW output
enable(OE) and three-state output drivers.
The BS616LV2025 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV2025 is available in DICE form and 48-pin BGA type.
PRODUCT FAMILY
PRODUCT
FAMILY
BS616LV2025DC
BS616LV2025AC
BS616LV2025DI
BS616LV2025AI
OPERATING
TEMPERATURE
+0 C to +70 C
-40 C to +85 C
O
O
O
O
Vcc
RANGE
4.5V ~ 5.5V
4.5V ~ 5.5V
SPEED
( ns )
Vcc=5.0V
POWER DISSIPATION
STANDBY
Operating
( I
CCSB1
, Max )
( I
CC
, Max )
PKG TYPE
DICE
BGA-48-0608
DICE
BGA-48-0608
Vcc=5.0V
Vcc=5.0V
70 / 55
70 / 55
6uA
25uA
40mA
45mA
PIN CONFIGURATION
BLOCK DIAGRAM
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
2048
D0
16(8)
Data
Input
Buffer
16(8)
Column I/O
Address
Input
Buffer
20
Row
Decoder
1024
Memory Array
1024 x 2048
.
.
.
.
D15
CE1
CE2
WE
OE
UB
LB
CIO
Vdd
Vss
.
.
.
.
Write Driver
16(8)
Sense Amp
128(256)
Column Decoder
16(8)
Data
Output
Buffer
14(16)
Control
Address Input Buffer
A16 A0 A1 A2 A3 A4 A5
(SAE)
Brilliance Semiconductor Inc
. reserves the right to modify document contents without notice.
R0201-BS616LV2025
1
Revision 2.4
April 2002

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