BSI
FEATURES
Very Low Power/Voltage CMOS SRAM
128K X 16 bit
BS616LV2017
鈥?Vcc operation voltage : 4.5V ~ 5.5V
鈥?Very low power consumption :
Vcc = 5.0V C-grade: 60mA (@55ns) operating current
I -grade: 62mA (@55ns) operating current
C-grade: 53mA (@70ns) operating current
I -grade: 55mA (@70ns) operating current
1.0uA(Typ.) CMOS standby current
鈥?High speed access time :
-55
55ns
-70
70ns
鈥?Automatic power down when chip is deselected
鈥?Three state outputs and TTL compatible
鈥?Fully static operation
鈥?Data retention supply voltage as low as 1.5V
鈥?Easy expansion with CE and OE options
鈥?I/O Configuration x8/x16 selectable by LB and UB pin
DESCRIPTION
The BS616LV2017 is a high performance , very low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits and
operates from a range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
1.0uA at 5.0V /25
o
C and maximum access time of 55ns at 5.0V / 85
o
C.
Easy memory expansion is provided by active LOW chip enable (CE),
active LOW output enable(OE) and three-state output drivers.
The BS616LV2017 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV2017 is available in DICE form , JEDEC standard 44-pin
TSOP Type II package and 48-ball BGA package.
PRODUCT FAMILY
PRODUCT
FAMILY
BS616LV2017DC
BS616LV2017EC
BS616LV2017AC
BS616LV2017DI
BS616LV2017EI
BS616LV2017AI
OPERATING
TEMPERATURE
Vcc
RANGE
SPEED
( ns )
55ns: 4.5~5.5V
70ns: 4.5~5.5V
( I
CCSB1
, Max )
Vcc=5.0V
POWER DISSIPATION
STANDBY
Operating
( I
CC
, Max )
Vcc=5.0V
55ns
70ns
PKG TYPE
DICE
TSOP2-44
BGA-48-0608
DICE
TSOP2-44
BGA-48-0608
+0
O
C to +70
O
C
4.5V ~5.5V
55/70
10uA
60mA
53mA
-40
O
C to +85
O
C
4.5V ~ 5.5V
55/70
30uA
62mA
55mA
PIN CONFIGURATIONS
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VCC
GND
DQ4
DQ5
DQ6
DQ7
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
GND
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
NC
BLOCK DIAGRAM
A8
A13
A15
A16
A14
A12
A7
A6
A5
A4
Address
Input
Buffer
20
Row
Decoder
1024
Memory Array
1024 x 2048
BS616LV2017EC
BS616LV2017EI
2048
DQ0
16
Data
Input
Buffer
16
Column I/O
1
A
B
C
D
E
F
G
H
LB
D8
D9
VSS
VCC
D14
D15
N.C.
2
OE
UB
D10
D11
D12
D13
N.C.
A8
3
A0
A3
A5
N.C.
N.C.
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CE
D1
D3
D4
D5
WE
A11
6
N.C.
D0
D2
VCC
VSS
D6
D7
N.C.
.
.
.
.
DQ15
.
.
.
.
Write Driver
Sense Amp
128
Column Decoder
16
Data
Output
16
Buffer
CE
WE
OE
UB
LB
Vcc
Gnd
Control
14
Address Input Buffer
A11 A9 A3 A2 A1 A0 A10
Brilliance Semiconductor, Inc
.
reserves the right to modify document contents without notice.
R0201-BS616LV2017
1
Revision 1.1
Jan.
2004
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