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BR93LC56FV Datasheet

  • BR93LC56FV

  • 2,048-Bit Serial Electrically Erasable PROM

  • 128.61KB

  • 12頁

  • ROHM

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Memory ICs
2,048-Bit Serial Electrically Erasable PROM
BR93LC56 / BR93LC56F / BR93LC56RF / BR93LC56FV
鈥?/div>
Features CMOS technology
鈥?Low power
鈥?128
脳
16 bit configuration
鈥?2.7V to 5.5V operation
鈥?Low power dissipation
鈥?3mA (max.) active current: 5V
鈥?5碌A(chǔ) (max.) standby current: 5V
鈥?Auto increment for efficient data bump
鈥?Automatic erase-before-write
鈥?Hardware and software write protection
鈥?Default to write-disabled state at power up
鈥?Software instructions for write-enable / disable
鈥?Vcc lock out inadvertent write protection
鈥?8-pin SOP / 8-pin SSOP-B / 8-pin DIP packages
鈥?Device status signal during write cycle
鈥?TTL compatible Input / Output
鈥?100,000 ERASE / write cycles
鈥?10 years Data Retention
鈥?/div>
Pin assignments
CS 1
SK 2
DI
3
8 V
CC
7 N.C.
N.C. 1
V
CC
2
CS
SK
3
4
8
7
6
5
N.C.
GND
DO
DI
BR93LC56 /
BR93LC56RF
6 N.C.
5 GND
BR93LC56F /
BR93LC56FV
DO 4
鈥?/div>
Pin descriptions
Pin
name
CS
SK
DI
DO
GND
N.C.
N.C.
V
CC
Chip select input
Serial clock input
Start bit, operating code, address, and serial
data input
Serial data output, READY / BUSY internal
status display output
Ground
Not connected
Not connected
Power supply
Function
鈥?/div>
Overview is CMOS serial input / output-type memory circuits (EEPROMs) that can be programmed electrically.
The BR93LC56
Each is configured of 128 words
脳
16 bits (2,048 bits), and each word can be accessed individually and data read
from it and written to it.
Operation control is performed using five types of commands. The commands, addresses, and data are input
through the DI pin under the control of the CS and SK pins. In a write operation, the internal status signal (READY or
BUSY) can be output from the DO pin.
The only difference between the BR93LC56 / F / RF / FV is the write disable voltage and its accompanying write
enable voltage. All other functions and characteristics are the same.
1

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