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BQ4285EP Datasheet

  • BQ4285EP

  • Enhanced RTC With NVRAM Control

  • 32頁(yè)

  • TI

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bq4285E/L
Enhanced RTC With NVRAM Control
Features
廬
Direct clock/calendar replace-
ment for IBM
廬
AT-compatible
computers and other applications
廬
114 bytes of general nonvolatile
storage
廬
Enhanced features include:
廬
BCD or binary format for clock
and calendar data
廬
Calendar in day of the week, day
of the month, months, and years,
with automatic leap-year adjust-
ment
廬
Time of day in seconds, minutes,
and hours
General Description
The CMOS bq4285E/L is a low-power
microprocessor peripheral providing a
time-of-day clock and 100-year calen-
dar with alarm features and battery
operation. Other features include
three maskable interrupt sources,
square wave output, and 114 bytes of
general nonvolatile storage.
A 32.768kHz output is available for
sustaining power-management activi-
ties. Wake-up capability is provided by
an alarm interrupt, which is active in
battery-backup mode.
The bq4285E/L write-protects the
clock, calendar, and storage registers
during power failure. A backup bat-
tery then maintains data and oper-
ates the clock and calendar.
The bq4285E/L is a fully compatible
re al-t ime clo ck fo r IB M AT-
compatible computers and other ap-
plications. The only external compo-
nents are a 32.768kHz crystal and a
backup battery.
The bq4285E/ L inte grate s a
battery-backup controller to make a
-
-
-
System wake-up capability鈥?/div>
alarm interrupt output active
in battery-backup mode
2.7鈥?.6V operation (bq4285L);
4.5鈥?.5V operation (bq4285E)
32kHz output for power
management
-
-
12- or 24-hour format
Optional daylight saving
adjustment
廬
Programmable square wave out-
put
廬
Three individually maskable in-
terrupt event flags:
廬
Automatic backup and write-
protect control to external SRAM
廬
Functionally compatible with the
DS1285
廬
Less than 0.5
碌A(chǔ)
load under bat-
tery operation
-
-
-
Periodic rates from 122碌s to
500ms
Time-of-day alarm once per
second to once per day
End-of-clock update cycle
廬
24-pin plastic DIP or SOIC
廬
14 bytes for clock/calendar and
control
Pin Connections
VOUT
X1
X2
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
VSS
Pin Names
AD
0
鈥揂D
7
MOT
Multiplexed address/data
input/output
Bus type select input
Chip select input
Address strobe input
Data strobe input
Read/write input
Interrupt request output
Reset input
Square wave output
3V backup cell input
Crystal inputs
No connect
RAM chip enable input
RAM chip enable output
Supply output
+5V supply
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
SQW
CEOUT
CEIN
BC
INT
RST
DS
VSS
R/W
AS
CS
24-Pin DIP or SOIC
PN428501.eps
28-Pin PLCC:
No Longer Available
CS
AS
DS
R/W
INT
RST
SQW
BC
X1鈥揦2
NC
CE
IN
CE
OUT
V
OUT
V
CC
SLUS006A - MAY
1994
- REVISED MAY 2004
1

BQ4285EP 產(chǎn)品屬性

  • Clock Basics in 10 minutes or less

  • 15

  • 集成電路 (IC)

  • 時(shí)鐘/計(jì)時(shí) - 實(shí)時(shí)時(shí)鐘

  • -

  • 時(shí)鐘/日歷

  • 警報(bào)器，夏令時(shí)，閏年，NVSRAM，方波輸出

  • 114B

  • HH:MM:SS（12/24 小時(shí)）

  • YY-MM-DD-dd

  • 并聯(lián)

  • 4.5 V ~ 5.5 V

  • 2.5 V ~ 4 V

  • 0°C ~ 70°C

  • 通孔

  • 24-DIP（0.600"，15.24mm）

  • 24-PDIP

  • 管件

  • 296-6525-5

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