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BQ2204ASNN Datasheet

  • BQ2204ASNN

  • X4 SRAM Nonvolatile Controller Unit

  • 12頁

  • TI

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bq2204A
X4 SRAM Nonvolatile Controller Unit
Features
General Description
The CMOS bq2204A SRAM Non-
volatile Controller Unit provides all
necessary functions for converting
up to four banks of standard CMOS
SRAM into nonvolatile read/write
memory.
A precision comparator monitors the 5V
V
CC
input for an out-of-tolerance condi-
tion. When out-of-tolerance is detected,
the four conditioned chip-enable outputs
are forced inactive to write-protect up to
four banks of SRAM.
盲
Power monitoring and switching
盲
Write-protect control
盲
2-input decoder for control of up
to 4 banks of SRAM
盲
3-volt primary cell inputs
盲
L e s s t ha n 10n s chi p-e nable
propagation delay
盲
5% or 10% supply operation
Pin Connections
VOUT
BC2
NC
A
B
NC
THS
VSS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
for 3-volt battery-backup applica-
tions
During a power failure, the external
SRAMs are switched from the V
CC
supply to one of two 3V backup sup-
plies. On a subsequent power-up, the
SRAMs are write-protected until a
power-valid condition exists.
During power-valid operation, a
two-input decoder transparently se-
lects one of up to four banks of
SRAM.
Pin Names
V
OUT
VCC
BC1
CE
CECON1
CECON2
CECON3
CECON4
NC
Supply output
3 volt primary backup cell inputs
Threshold select input
chip-enable active low input
Conditioned chip-enable outputs
Decoder inputs
No connect
+5 volt supply input
Ground
BC
1
鈥揃C
2
THS
CE
CE
CON1
鈥?/div>
CE
CON4
A鈥揃
NC
V
CC
V
SS
16-Pin Narrow DIP or SOIC
PN220401.eps
Functional Description
Up to four banks of CMOS static RAM can be battery-
backed using the V
OUT
and conditioned chip-enable out-
put pins from the bq2204A. As V
CC
slews down during
a power failure, the conditioned chip-enable outputs
CE
CON1
through CE
CON4
are forced inactive independ-
ent of the chip-enable input CE.
This activity unconditionally write-protects the external
SRAM as V
CC
falls below an out-of-tolerance threshold
V
PFD
. V
PFD
is selected by the threshold select input pin,
THS. If THS is tied to V
SS
, the power-fail detection occurs
at 4.62V typical for 5% supply operation.
Dec. 1992 B
If THS is tied to V
CC
, power-fail detection occurs at
4.37V typical for 10% supply operation. The THS pin
must be tied to V
SS
or V
CC
for proper operation.
If a memory access is in process to any of the four external
banks of SRAM during power-fail detection, that memory
cycle continues to completion before the memory is write-
protected. If the memory cycle is not terminated within
time t
WPT
, all four chip-enable outputs are unconditionally
driven high, write-protecting the controlled SRAMs.
1

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