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BQ2201PNN Datasheet

  • BQ2201PNN

  • SRAM Nonvolatile Controller Unit

  • 12頁(yè)

  • TI

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bq2201
SRAM Nonvolatile Controller Unit
Features
廬
Power monitoring and switching
for 3-volt battery-backup applica-
tions
廬
Write-protect control
廬
3-volt primary cell inputs
廬
L e s s th an 10 ns chip- e nabl e
propagation delay
廬
5% or 10% supply operation
General Description
The CMOS bq2201 SRAM Nonvolatile
Controller Unit provides all necessary
functions for converting a standard
CMOS SRAM into nonvolatile
read/write memory.
A precision comparator monitors the
5V V
CC
input for an out-of-tolerance
condition. When out of tolerance is
detected, a conditioned chip-enable
output is forced inactive to write-
protect any standard CMOS SRAM.
During a power failure, the external
SRAM is switched from the V
CC
supply to one of two 3V backup sup-
plies. On a subsequent power-up, the
SRAM is write-protected until a
power-valid condition exists.
The bq2201 is footprint- and timing-
compatible with industry stan-
dards with the added benefit of a
chip-enable propagation delay of
less than 10ns.
Pin Connections
Pin Names
V
OUT
BC
1
鈥擝C
2
NC
V
OUT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NC
Supply output
3-volt primary backup cell inputs
Threshold select input
chip-enable active low input
Conditioned chip-enable output
+5-volt supply input
Ground
No Connect
THS
V
CC
NC
BC
1
NC
CE
CON
NC
CE
VOUT
BC2
THS
VSS
1
2
3
4
8
7
6
5
VCC
BC1
CECON
CE
NC
BC
2
NC
THS
NC
CE
CE
CON
V
CC
V
SS
NC
8-Pin Narrow DIP or SOIC
PN220101.eps
VSS
16-Pin SOIC
PN2201E.eps
Functional Description
An external CMOS static RAM can be battery-backed
using the V
OUT
and the conditioned chip-enable output
pin from the bq2201. As V
CC
slews down during a power
failure, the conditioned chip-enable output CE
CON
is
forced inactive independent of the chip-enable input CE.
This activity unconditionally write-protects external
SRAM as V
CC
falls to an out-of-tolerance threshold V
PFD
.
V
PFD
is selected by the threshold select input pin, THS.
If THS is tied to V
SS
, power-fail detection occurs at 4.62V
typical for 5% supply operation. If THS is tied to V
CC
,
power-fail detection occurs at 4.37V typical for 10% sup-
ply operation. The THS pin must be tied to V
SS
or V
CC
for
proper operation.
If a memory access is in process during power-fail detec-
tion, that memory cycle continues to completion before the
memory is write-protected. If the memory cycle is not ter-
minated within time t
WPT
, the CE
CON
output is uncondi-
tionally driven high, write-protecting the memory.
Oct. 1998 D
1

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