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BQ2018SN Datasheet

  • BQ2018SN

  • Power Minder⑩ IC

  • 21頁

  • TI

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bq2018
Power Minder鈩?IC
Features
廬
Multifunction charge/discharge
counter
廬
Resolves signals less than 12.5碌V
廬
Internal offset calibration im-
proves accuracy
廬
1024 bits of NVRAM configured as
128 x 8
廬
Internal temperature sensor for
self-discharge estimation
廬
Single-wire serial interface
廬
Dual operating modes:
General Description
The bq2018 is a low-cost charge/dis-
charge counter peripheral packaged in
an 8-pin TSSOP or SOIC. It works
with an intelligent host controller, pro-
viding state-of-charge information for
rechargeable batteries.
The bq2018 measures the voltage
drop across a low-value series sense
resistor between the negative termi-
nal of the battery and the battery
pack ground contact. By using the ac-
cumulated counts in the charge,
discharge, and self-discharge regis-
ters, an intelligent host controller can
determine battery state-of-charge in-
formation. To improve accuracy, an
offset count register is available. The
system host controller is responsible
for the register maintenance by reset-
ting the charge in/out and self-
discharge registers as needed.
The bq2018 also features 128 bytes
of NVRAM registers. The upper 13
bytes of NVRAM contain the capac-
ity monitoring and status informa-
tion. The RBI input operates from
an external power storage source
such as a capacitor or a series cell in
the battery pack, providing register
nonvolatility for periods when the
battery is shorted to ground or when
the battery charge state is not suffi-
cient to operate the bq2018. During
this mode, the register backup cur-
rent is less than 100nA.
Packaged in an 8-pin TSSOP or
SOIC, the bq2018 is small enough
to fit in the crevice between two A-
size cells or within the width of a
prismatic cell.
-
-
Operating: <80碌A
Sleep: <10碌A
廬
REG output for low-cost mi-
croregulation
廬
Internal timebase eliminates ex-
ternal components
廬
8-pin TSSOP or SOIC allows bat-
tery pack integration
Pin Connections
Pin Names
REG
V
CC
Regulator output
Supply voltage input
Ground
Data input/output
WAKE
SR1
SR2
RBI
Wake-up output
Current sense input 1
Current sense input 2
Register backup input
REG
VCC
VSS
HDQ
1
2
3
4
8
7
6
5
WAKE
SR1
SR2
RBI
V
SS
HDQ
8-Pin TSSOP or Narrow SOIC
PN-201801.eps
SLUS003鈥揓UNE 1999 C
1

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