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AZ62P44 Datasheet

  • AZ62P44

  • DUAL CHANNEL, 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/...

  • 70頁

  • TI

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ADS62P45, ADS62P44
ADS62P43, ADS62P42
SLAS561A 鈥?JULY 2007 鈥?REVISED FEBRUARY 2008
DUAL CHANNEL, 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS
1
FEATURES
Maximum Sample Rate: 125 MSPS
14-Bit Resolution with No Missing Codes
95 dB Crosstalk
Parallel CMOS and DDR LVDS Output Options
3.5 dB Coarse Gain and Programmable Fine
Gain up to 6 dB for SNR/SFDR Trade-Off
Digital Processing Block
with:
鈥?Offset Correction
鈥?Fine Gain Correction, in Steps of 0.05 dB
鈥?Decimation by 2/4/8
鈥?Built-in and Custom Programmable 24-Tap
Low-/High-/Band-Pass Filters
Supports Sine, LVPECL, LVDS and LVCMOS
Clocks and Amplitude Down to 400 mV
PP
Clock Duty Cycle Stabilizer
Internal Reference; Supports External
Reference also
64-QFN Package (9mm
9mm)
Pin Compatible 12-Bit Family (ADS62P2X)
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DESCRIPTION
ADS62P4X is a dual channel 14-bit A/D converter
family with maximum sample rates up to 125 MSPS.
It combines high performance and low power
consumption in a compact 64 QFN package. Using
an internal sample and hold and low jitter clock
buffer, the ADC supports high SNR and high SFDR at
high input frequencies. It has coarse and fine gain
options that can be used to improve SFDR
performance at lower full-scale input ranges.
ADS62P4X includes a digital processing block that
consists of several useful and commonly used digital
functions such as ADC offset correction, fine gain
correction (in steps of 0.05 dB), decimation by 2,4,8
and in-built and custom programmable filters. By
default, the digital processing block is bypassed, and
its functions are disabled.
Two output interface options exist 鈥?parallel CMOS
and DDR LVDS (Double Data Rate). ADS62P4X
includes internal references while traditional
reference pins and associated decoupling capacitors
have been eliminated. Nevertheless, the device can
also be driven with an external reference. The device
is specified over the industrial temperature range
(鈥?0擄C to 85擄C).
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APPLICATIONS
Wireless Communications Infrastructure
Software Defined Radio
Power Amplifier Linearization
802.16d/e
Medical Imaging
Radar Systems
Test and Measurement Instrumentation
ADS62P4X Performance Summary
ADS62P45
SFDR, dBc
SINAD, dBFS
F
in
= 10 MHz (0 dB gain)
F
in
= 190 MHz (3.5 dB gain)
F
in
= 10 MHz (0 dB gain)
F
in
= 190 MHz (3.5 dB gain)
88
84
73.7
70.8
799
ADS62P44
92
86
74.2
71
710
ADS62P43
93
87
74.6
71.3
594
ADS62P42
94
85
74.7
70.9
515
Analog Power, mW
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright 漏 2007鈥?008, Texas Instruments Incorporated

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  • 英文版
    DUAL CHANNEL, 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/...
    TI
  • 英文版
    DUAL CHANNEL, 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/...
    TI [Texas ...
  • 英文版
    DUAL CHANNEL, 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/...
    TI
  • 英文版
    DUAL CHANNEL, 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/...
    TI [Texas ...
  • 英文版
    DUAL CHANNEL, 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/...
    TI
  • 英文版
    DUAL CHANNEL, 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/...
    TI [Texas ...
  • 英文版
    DUAL CHANNEL, 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/...
    TI
  • 英文版
    DUAL CHANNEL, 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/...
    TI [Texas ...
  • 英文版
    REVERSIBLE MOTOR DRIVER
    BCD Semiconduct...
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    REVERSIBLE MOTOR DRIVER
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    REVERSIBLE MOTOR DRIVER
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    REVERSIBLE MOTOR DRIVER
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