鈥?/div>
鈥?86 Inputs and 72 Sum Terms
Flexible Output Macrocell
鈥?48 Flip-Flops - 2 per Macrocell
鈥?3 Sum Terms - Can Be OR'ed and Shared
High-Speed
Low-Power 鈥?Less than 0.5 mA Typical (ATV2500L)
Multiple Feedback Paths Provide for Buried State Machines
and I/O Bus Compatibility
Asynchronous Clocks and Resets
鈥?Multiple Synchronous Presets - One per Four or Eight Flip-Flops
Proven and Reliable High Speed CMOS EPROM Process
鈥?2000V ESD Protection
鈥?200 mA Latchup Immunity
Reprogrammable - Tested 100% for Programmability
40-pin Dual-In-line and 44-Lead Surface Mount Packages
High-Density
UV-Erasable
Programmable
Logic Device
ATV2500H
ATV2500L
Block Diagram
Description
The ATV2500H/L is the most powerful programmable logic device available in a 40-
pin package. Increased product terms, sum terms, and flip-flops translate into many
more usable gates. High gate utilization is easily obtainable.
The ATV2500H/L is organized around a global bus. All pin and feedback terms are
always available to every logic cell. Each of the 38 logic pins and their complements
are array inputs, as well as the true and false outputs of each of the 48 flip-flops.
(continued)
Pin Configurations
Pin Name
IN
I/O
I/O, 0,2,4..
I/O, 1,3,5..
*
VCC
Function
Logic Inputs
Bidirectional Buffers
鈥淓ven鈥?I/O Buffers
鈥淥dd鈥?I/O Buffers
No Internal Connection
+5V Supply
IN
IN
IN
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
VCC
I/O17
I/O16
I/O15
I/O14
I/O13
I/O12
IN
IN
IN
IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DIP
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
IN
IN
IN
IN
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
GND
I/O23
I/O22
I/O21
I/O20
I/O19
I/O18
IN
IN
IN
PLCC/LCC
I/O1
I/O0
*
IN
IN
IN
IN
IN
IN
IN
I/O06
6
5
4
3
2
1
44
43
42
41
40
* = No Connect
Rev. 0025E鈥?5/98
I/O12
IN
IN
IN
IN
IN
IN
IN
*
I/O18
I/O19
18
19
20
21
22
23
24
25
26
27
28
I/O2
I/O3
I/O4
I/O5
VCC
VCC
I/O17
I/O16
I/O15
I/O14
I/O13
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
I/O7
I/O8
I/O9
I/O10
I/O11
GND
GND
I/O23
I/O22
I/O21
I/O20
1