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Specifically Designed for Battery Powered Applications
1.0 - 3.0 Volts and will Operate from 0.7 to 5.5 Volts
Static Current Drain of <75 nA at 1.0 Volts
200 MHz Maximum Toggle Frequency for Flip Flop at 1.5 Volts
1.0
碌
Drawn Gate Length CMOS Gate Arrays
All Package Styles Offered Including TQFP and TAB
Improved Product Testability Using Serial Scan, Boundary Scan,
and JTAG
Second Source Existing ASIC Design in Atmel's ATLV via Design
Translation. Improved Performance and Lower Cost
Description
The ATLV Series CMOS gate arrays employ 1.0
碌-drawn,
double-level metal,
Si-gate, CMOS technology processed in Atmel's U.S.-based, advanced
manufacturing facility. The arrays utilize an enhanced channelless architecture
which results in greater than 50 percent usable gates.
Atmel's flexible design system uses industry design standards and is compatible
with popular CAD/CAE software and hardware packages. The customer can
start designing with the ATLV series today using existing CAD/CAE tools.
ATLV Series
Ultra Low
Voltage
Gate Arrays
ATLV2
ATLV3
ATLV5
ATLV7
ATLV10
ATLV15
ATLV20
ATLV35
ATLV Array Organization
Device
Number
ATLV2
ATLV3
ATLV5
ATLV7
ATLV10
ATLV15
ATLV20
ATLV35
Raw
Gates
2,000
3,000
5,000
7,000
10,000
15,000
22,000
35,000
Routable
Gates
1,400
1,600
2,800
4,400
6,600
8,000
12,000
18,000
Max Pin
Count
44
68
84
100
120
144
160
208
Max I/O
(1)
Pins
36
60
76
92
112
136
152
192
Gate
(2)
Speed
1.3 ns
1.3 ns
1.3 ns
1.3 ns
1.3 ns
1.3 ns
1.3 ns
1.3 ns
Notes: 1. Absolute maximum I/O pins is maximum pin count minus 8. Additional power
and ground pins are assumed to be required to support simultaneous
switching outputs as pin count increases.
2. Nominal 2 input nand gate with a fan out of 2 at 1.5 volts, room temperature.
0261B
1