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ATL60/300 Datasheet

  • ATL60/300

  • FPGA

  • 14頁

  • ETC

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Features
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0.6 碌m Drawn Gate Length (0.5 碌m Leff) Sea-of-Gates Architecture
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with Triple-level Metal
5.0V, 3.3V and 2.0V Operation including Mixed Voltages
On-chip Phase Locked Loop Available to Synthesize Frequencies up to 150 MHz and
Manage Chip-to-Chip Clock Skew
Compiled (Gate Level) and Embedded (Custom) SRAMs, ROM, and CAMs Available
PCI, SCSI and High Speed (250 MHz) Buffers Available
Easy Alternative Sourcing of Existing ASIC, FPGA and PLD Designs
Design-for-Test Methods, Including JTAG, Serial and Boundary Scan and ATPG
High Output Drive Capability: Up to 48 mA with Slew Rate Control
ASIC
ATL 60 and
ATLS60 Series
Description
Atmel鈥檚 next generation ATL60 Series CMOS ASICs are fabricated using a 0.6碌m
drawn gate, oxide isolated, triple-level metal process. Extensive cell libraries are avail-
able and support the major CAD software tools. As with all Atmel ASIC families,
customer involvement and satisfaction is integral to all steps of the design flow. A vari-
ety of Design for Testability techniques are supported by the libraries, and a wide
range of packaging options are available. The ATLS version utilizes a fine pitch stag-
gered row on bond pads to achieve the smallest die size possible for a given pad
count. The ATLS60 is only available in a limited number of PQFP packages.
Table 1.
ATL60 Array Organization
Device
Number
ATL60/4
ATL60/15
ATL60/25
ATL60/40
ATL60/60
ATL60/85
ATL60/110
ATL60/150
ATL60/200
ATL60/235
ATL60/300
ATL60/435
ATL60/550
ATL60/700
ATL60/870
ATL60/1100
Note:
Raw
Gates
4,000
15,000
25,000
38,000
58,000
86,000
110,000
149,000
195,000
232,000
301,000
430,000
545,000
693,000
870,000
1,119,000
Routable
Gates
3,000
10,000
16,900
25,400
34,600
51,900
65,900
89,300
116,900
139,500
181,000
260,000
288,000
363,000
456,000
590,000
Max Pin
Count
44
68
84
100
120
144
160
184
208
226
256
304
340
380
424
480
Max I/O
Pins
36
60
76
92
112
136
152
176
200
218
248
296
332
372
416
472
Gate
(1)
Speed
200 ps
200 ps
200 ps
200 ps
200 ps
200 ps
200 ps
200 ps
200 ps
200 ps
200 ps
200 ps
200 ps
200 ps
200 ps
200 ps
1. Nominal two input NAND gate with a fanout of 2 at 5.0 volts
Rev. 0388D鈥揂SIC鈥?7/02
1

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