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ATF22V10CZ-12XC Datasheet

  • ATF22V10CZ-12XC

  • Highperformance EE PLD

  • 13頁

  • ATMEL   ATMEL

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Features
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Industry-standard Architecture
12 ns Maximum Pin-to-pin Delay
Zero Power 鈥?25
碌
A Maximum Standby Power (Input Transition Detection)
CMOS and TTL Compatible Inputs and Outputs
Advanced Electrically-erasableTechnology
鈥?Reprogrammable
鈥?100% Tested
Latch Feature Holds Inputs to Previous Logic State
High-reliability CMOS Process
鈥?20 Year Data Retention
鈥?100 Erase/Write Cycles
鈥?2,000V ESD Protection
鈥?200 mA Latchup Immunity
Commercial and Industrial Temperature Ranges
Dual-in-line and Surface Mount Standard Pinouts
PCI Compliant
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High-
performance
EE PLD
ATF22V10CZ
ATF22V10CQZ
Block Diagram
Description
The ATF22V10CZ/CQZ is a high-performance CMOS (electrically-erasable)
programmable logic device (PLD) which utilizes Atmel鈥檚 proven electrically-erasable
(continued)
Pin Configurations
All Pinouts Top View
Pin Name
CLK
IN
I/O
VCC
Function
Clock
Logic Inputs
TSSOP
CLK/IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
Bi-directional Buffers
+5V Supply
PLCC
IN
IN
CLK/IN
VCC*
VCC
I/O
I/O
4
3
2
1
28
27
26
DIP/SOIC
I/O
I/O
I/O
GND*
I/O
I/O
I/O
IN
IN
GND
GND*
IN
I/O
I/O
12
13
14
15
16
17
18
IN
IN
IN
GND*
IN
IN
IN
5
6
7
8
9
10
11
25
24
23
22
21
20
19
Note:
For PLCC, P1, P8, P15 and P22 can be left
unconnected. For superior performance, con-
nect VCC to pin 1 and GND to 8, 15, and 22.
CLK/IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
Rev. 0778H鈥?3/01
1

ATF22V10CZ-12XC 產(chǎn)品屬性

  • 5,000

  • 集成電路 (IC)

  • 嵌入式 - PLD（可編程邏輯器件）

  • 22V10

  • EE PLD

  • 10

  • 5V

  • 12ns

  • 表面貼裝

  • 24-TSSOP（0.173"，4.40mm 寬）

  • 24-TSSOP

  • 管件

  • ATF22V10CZ12XC

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