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Industry Standard Architecture
Emulates Many 20-Pin PALs
廬
Low Cost Easy-to-Use Software Tools
High Speed Electrically Erasable Programmable Logic Devices
5 ns Maximum Pin-to-Pin Delay
Low Power - 100
碌A
Pin-Controlled Power Down Mode Option
CMOS and TTL Compatible Inputs and Outputs
I/O Pin Keeper Circuits
Advanced Flash Technology
Reprogrammable
100% Tested
High Reliability CMOS Process
20 Year Data Retention
100 Erase/Write Cycles
2,000V ESD Protection
200 mA Latchup Immunity
Commercial and Industrial Temperature Ranges
Dual-in-Line and Surface Mount Packages in Standard Pinouts
High
Performance
E
2
PLD
ATF16V8C
Block Diagram
Note:
1. Includes optional PD control pin.
Pin Configurations
Pin Name
CLK
I
I/O
OE
VCC
PD
Function
Clock
Logic Inputs
Bidirectional Buffers
Output Enable
+5V Supply
Power Down
I/CLK
I1
I2
PD/I3
I4
I5
I6
I7
I8
GND
1
2
3
4
5
6
7
8
9
10
TSSOP Top View
ATF16V8C
20
19
18
17
16
15
14
13
12
11
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I9/OE
DIP/SOIC
PLCC
Top view
Rev. 0425D/V16FC-D鈥?4/98