鈥?/div>
Industry Standard Architecture
Emulates Many 20-Pin PALs
廬
Low Cost Easy-to-Use Software Tools
High Speed Electrically Erasable Programmable Logic Devices
12 ns Maximum Pin-to-Pin Delay
Low Power - 25
碌A(chǔ)
Standby Power
CMOS and TTL Compatible Inputs and Outputs
Input and I/O Pin Keeper Circuits
Advanced Flash Technology
Reprogrammable
100% Tested
High Reliability CMOS Process
20 Year Data Retention
100 Erase/Write Cycles
2,000V ESD Protection
200 mA Latchup Immunity
Commercial and Industrial Temperature Ranges
Dual Inline and Surface Mount Packages in Standard Pinouts
High
Performance
E
2
PLD
ATF16V8CZ
Block Diagram
Pin Configurations
Pin Name
CLK
I
I/O
OE
VCC
Function
Clock
Logic Inputs
Bidirectional Buffers
Output Enable
+5V Supply
I/CLK
I1
I2
I3
I4
I5
I6
I7
I8
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I9/OE
TSSOP Top View
ATF16V8CZ
DIP/SOIC
I/CLK
I1
I2
I3
I4
I5
I6
I7
I8
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Vcc
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I9/OE
I8
I3
I4
I5
I6
I7
6
PLCC
I2 I1
I/CLK Vcc
I/O
1
I/O
16
I/O
I/O
I/O
I/O
I/O I/O
11
GND I9/OE
Top view
Rev. 0453C/V16FZ-C鈥?4/98