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High Density, High Performance Electrically Erasable Complex
Programmable Logic Device
鈥?256 Macrocells
鈥?5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
鈥?160, 192, 208-pins
鈥?10 ns Maximum Pin-to-Pin Delay
鈥?Registered Operation Up To 100 MHz
鈥?Enhanced Routing Resources
Flexible Logic Macrocell
鈥?D/T/Latch Configurable Flip Flops
鈥?Global and Individual Register Control Signals
鈥?Global and Individual Output Enable
鈥?Programmable Output Slew Rate
鈥?Programmable Output Open Collector Option
鈥?Maximum Logic utilization by burying a register within a COM output
Advanced Power Management Features
鈥?Automatic 3 mA Stand-By for 鈥淟鈥?Version (Max.)
鈥?Pin-Controlled 4 mA Stand-By Mode (Typical)
鈥?Programmable Pin-Keeper Inputs and I/Os
鈥?Reduced-Power Feature Per Macrocell
Available in Commercial and Industrial Temperature Ranges
Available in 160-pin PQFP, 192 PGA and 208-pin RQFP Packages
Advanced EE Technology
鈥?100% Tested
鈥?Completely Reprogrammable
鈥?100 Program/Erase Cycles
鈥?20 Year Data Retention
鈥?2000V ESD Protection
鈥?200 mA Latch-Up Immunity
JTAG Boundary-Scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
Fast In-System Programmability (ISP) via JTAG
PCI-compliant
3.3 or 5.0V I/O pins
Security Fuse Feature
鈥?/div>
High
Performance
EE-Based CPLD
ATF1516AS/L
Preliminary
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鈥?/div>
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Enhanced Features
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Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
Output Enable Product Terms
D - Latch Mode
Combinatorial Output with Registered Feedback within any Macrocell
Three Global Clock Pins
ITD ( Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
Fast Registered Input from Product Term
Programmable 鈥淧in-Keeper鈥?Option
V
CC
Power-Up Reset Option
Pull-Up Option on JTAG Pins TMS and TDI
Advanced Power Management Features
鈥?Edge Controlled Power Down 鈥淟鈥?/div>
鈥?Individual Macrocell Power Option
鈥?Disable ITD on Global Clocks, Inputs and I/O
Rev. 0994A-A鈥?1/98
1
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