鈥?/div>
High-density, High-performance, Electrically-erasable
Complex Programmable Logic Device
鈥?3.0 to 3.6V Operating Range
鈥?64 Macrocells
鈥?5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
鈥?44, 68, 84, 100 Pins
鈥?15 ns Maximum Pin-to-pin Delay
鈥?Registered Operation up to 77 MHz
鈥?Enhanced Routing Resources
In-System Programmability (ISP) via JTAG
Flexible Logic Macrocell
鈥?D/T/Latch Configurable Flip-flops
鈥?Global and Individual Register Control Signals
鈥?Global and Individual Output Enable
鈥?Programmable Output Slew Rate
鈥?Programmable Output Open-collector Option
鈥?Maximum Logic Utilization by Burying a Register with a COM Output
Advanced Power Management Features
鈥?Automatic 5 碌A Standby for 鈥淟鈥?Version
鈥?Pin-controlled 100 碌A Standby Mode (Typical)
鈥?Programmable Pin-keeper Circuits on Inputs and I/Os
鈥?Reduced-power Feature per Macrocell
Available in Commercial and Industrial Temperature Ranges
Available in 44-, 68-, and 84-lead PLCC; 44- and 100-lead TQFP; and 100-lead PQFP
Advanced EE Technology
鈥?100% Tested
鈥?Completely Reprogrammable
鈥?10,000 Program/Erase Cycles
鈥?20 Year Data Retention
鈥?2000V ESD Protection
鈥?200 mA Latch-up Immunity
JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
PCI-compliant
Security Fuse Feature
鈥?/div>
鈥?/div>
鈥?/div>
Low-voltage,
Complex
Programmable
Logic Device
ATF1504ASV
ATF1504ASVL
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Enhanced Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
Output Enable Product Terms
Transparent-latch Mode
Combinatorial Output with Registered Feedback within Any Macrocell
Three Global Clock Pins
ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
Fast Registered Input from Product Term
Programmable 鈥淧in-keeper鈥?Option
V
CC
Power-up Reset Option
Pull-up Option on JTAG Pins TMS and TDI
Advanced Power Management Features
鈥?Edge-controlled Power-down 鈥淟鈥?/div>
鈥?Individual Macrocell Power Option
鈥?Disable ITD on Global Clocks, Inputs and I/O
Rev. 1409F鈥?9/00
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