512 Kbits to 1 Mbit of Configuration Memory with Security Protection and In-System
鈩?/div>
鈥?2 - 18.4 Kbits of Distributed Single/Dual Port FPGA User SRAM
鈥?High-performance DSP Optimized FPGA Core Cell
鈥?Dynamically Reconfigurable In-System 鈥?FPGA Configuration Access Available
On-chip from AVR Microcontroller Core to Support Cache Logic
廬
Designs
鈥?Very Low Static and Dynamic Power Consumption 鈥?Ideal for Portable and
Handheld Applications
Patented AVR Enhanced RISC Architecture
鈥?120+ Powerful Instructions 鈥?Most Single Clock Cycle Execution
鈥?High-performance Hardware Multiplier for DSP-based Systems
鈥?Approaching 1 MIPS per MHz Performance
鈥?C Code Optimized Architecture with 32 x 8 General-purpose Internal Registers
鈥?Low-power Idle, Power-save, and Power-down Modes
鈥?100 碌A(chǔ) Standby and Typical 2-3 mA per MHz Active
Up to 36 Kbytes of Dynamically Allocated Instruction and Data SRAM
鈥?Up to 16 Kbytes x 16 Internal 15 ns Instructions SRAM
鈥?Up to 16 Kbytes x 8 Internal 15 ns Data SRAM
JTAG (IEEE Std. 1149.1 Compliant) Interface
鈥?Extensive On-chip Debugging Support
鈥?Limited Boundary-scan Capabilities According to the JTAG Standards (AVR Ports)
AVR Fixed Peripherals
鈥?Industry-standard 2-wire Serial Interface
鈥?Two Programmable Serial UARTs
鈥?Two 8-bit Timer/Counters with Separate Prescaler and PWM
鈥?One 16-bit Timer/Counter with Separate Prescaler, Compare, Capture
Modes and Dual 8-, 9- or 10-bit PWM
Support for FPGA Custom Peripherals
鈥?AVR Peripheral Control 鈥?Up to 16 Decoded AVR Address Lines Directly
Accessible to FPGA
鈥?FPGA Macro Library of Custom Peripherals
Up to 16 FPGA Supplied Internal Interrupts to AVR
Up to Four External Interrupts to AVR
8 Global FPGA Clocks
鈥?Two FPGA Clocks Driven from AVR Logic
鈥?FPGA Global Clock Access Available from FPGA Core
Multiple Oscillator Circuits
鈥?Programmable Watchdog Timer with On-chip Oscillator
鈥?Oscillator to AVR Internal Clock Circuit
鈥?Software-selectable Clock Frequency
鈥?Oscillator to Timer/Counter for Real-time Clock
V
CC
: 3.0V - 3.6V
5V Tolerant I/O
3.3V 33 MHz PCI Compliant FPGA I/O
鈥?20 mA Sink/Source High-performance I/O Structures
鈥?All FPGA I/O Individually Programmable
High-performance, Low-power 0.35碌 CMOS Five-layer Metal Process
State-of-the-art Integrated PC-based Software Suite including Co-verification
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Secure
5K - 40K Gates
of AT40K FPGA
with 8-bit
Microcontroller,
up to 36 Kbytes
of SRAM and
On-chip
Program
Storage
EEPROM
AT94S
Secure Series
Programmable
SLI
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Rev. 2314D鈥揊PSLI鈥?/04
1
next
AT94S40AL相關(guān)型號PDF文件下載
-
型號
版本
描述
廠商
下載
-
英文版
Secure 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroll...
-
英文版
Secure 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroll...
ATMEL [ATM...
-
英文版
5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller, up ...
-
英文版
5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller, up ...
ATMEL [ATM...
-
英文版
Secure 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroll...
-
英文版
Secure 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroll...
ATMEL [ATM...
-
英文版
COVER SPLASH RND LB PNL SEAL SER
-
英文版
5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller, up ...
-
英文版
MYLAR/POLYESTER FILM
-
英文版
MYLAR/POLYESTER FILM
-
英文版
5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller, up ...
-
英文版
Secure 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroll...
-
英文版
Secure 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroll...
ATMEL [ATM...
-
英文版
Secure 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroll...
-
英文版
Secure 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroll...
ATMEL [ATM...
-
英文版
Secure 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroll...
-
英文版
Secure 5K - 40K Gates of AT40K FPGA with 8-bit Microcontroll...
ATMEL [ATM...
-
英文版
-
英文版
5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller,up t...
-
英文版
5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller,up t...