AT94K10AL-25AQC Datasheet

IC型號：
AT94K10AL-25AQC
PDF描述：
5K - 40K Gates of AT40K FPGA with 8-bit Microcontroller, up ...
文件大?。?/label>
1574.06KB
PDF頁數(shù)：
192頁
芯片廠家：
ATMEL

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Features

鈥?/div>

Monolithic Field Programmable System Level Integrated Circuit (FPSLIC

鈩?/div>

)

鈥?/div>

鈥?AT40K SRAM-based FPGA with Embedded High-performance RISC AVR

廬

Core,

Extensive Data and Instruction SRAM and JTAG ICE

5,000 to 40,000 Gates of Patented SRAM-based AT40K FPGA with FreeRAM

鈩?/div>

鈥?2 - 18.4 Kbits of Distributed Single/Dual Port FPGA User SRAM

鈥?High-performance DSP Optimized FPGA Core Cell

鈥?Dynamically Reconfigurable In-System 鈥?FPGA Configuration Access Available

On-chip from AVR Microcontroller Core to Support Cache Logic

廬

Designs

鈥?Very Low Static and Dynamic Power Consumption 鈥?Ideal for Portable and

Handheld Applications

Patented AVR Enhanced RISC Architecture

鈥?120+ Powerful Instructions 鈥?Most Single Clock Cycle Execution

鈥?High-performance Hardware Multiplier for DSP-based Systems

鈥?Approaching 1 MIPS per MHz Performance

鈥?C Code Optimized Architecture with 32 x 8 General-purpose Internal Registers

鈥?Low-power Idle, Power-save and Power-down Modes

鈥?100 碌A Standby and Typical 2-3 mA per MHz Active

Up to 36 Kbytes of Dynamically Allocated Instruction and Data SRAM

鈥?Up to 16 Kbytes x 16 Internal 15 ns Instructions SRAM

鈥?Up to 16 Kbytes x 8 Internal 15 ns Data SRAM

JTAG (IEEE std. 1149.1 Compliant) Interface

鈥?Extensive On-chip Debug Support

鈥?Limited Boundary-scan Capabilities According to the JTAG Standard (AVR Ports)

AVR Fixed Peripherals

鈥?Industry-standard 2-wire Serial Interface

鈥?Two Programmable Serial UARTs

鈥?Two 8-bit Timer/Counters with Separate Prescaler and PWM

鈥?One 16-bit Timer/Counter with Separate Prescaler, Compare, Capture

Modes and Dual 8-, 9- or 10-bit PWM

Support for FPGA Custom Peripherals

鈥?AVR Peripheral Control 鈥?16 Decoded AVR Address Lines Directly Accessible

to FPGA

鈥?FPGA Macro Library of Custom Peripherals

16 FPGA Supplied Internal Interrupts to AVR

Up to Four External Interrupts to AVR

8 Global FPGA Clocks

鈥?Two FPGA Clocks Driven from AVR Logic

鈥?FPGA Global Clock Access Available from FPGA Core

Multiple Oscillator Circuits

鈥?Programmable Watchdog Timer with On-chip Oscillator

鈥?Oscillator to AVR Internal Clock Circuit

鈥?Software-selectable Clock Frequency

鈥?Oscillator to Timer/Counter for Real-time Clock

: 3.0V - 3.6V

3.3V 33 MHz PCI-compliant FPGA I/O

鈥?20 mA Sink/Source High-performance I/O Structures

鈥?All FPGA I/O Individually Programmable

High-performance, Low-power 0.35碌 CMOS Five-layer Metal Process

State-of-the-art Integrated PC-based Software Suite including Co-verification

5V I/O Tolerant

鈥?/div>

5K - 40K Gates

of AT40K FPGA

with 8-bit

Microcontroller,

up to 36K Bytes

of SRAM and

On-chip

JTAG ICE

AT94K Series

Field

Programmable

System Level

Integrated

Circuit

鈥?/div>

Rev. 1138F鈥揊PSLI鈥?6/02

標準包裝
96
類別
集成電路 (IC)
家庭
嵌入式 - 帶有微控制器的 FPGA（現(xiàn)場可編程門陣列）
系列
FPSLIC®
內核類型
8 位 AVR
速度
25MHz
接口
I²C，UART
程序 SRAM 字節(jié)
20K-32K
FPGA SRAM
4kb
EEPROM 大小
-
數(shù)據(jù) SRAM 字節(jié)
4K ~ 16K
FPGA 內核單元
576
FPGA 門
10K
FPGA 寄存器
846
電源電壓
3 V ~ 3.6 V
安裝類型
表面貼裝
工作溫度
0°C ~ 70°C
封裝/外殼
100-TQFP
供應商設備封裝
100-TQFP（14x14）
包裝
托盤
配用
ATSTK594-ND - BOARD FPSLIC DAUGHTER FOR STK500

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