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MPEGI/II-Layer 3 Hardwired Decoder
鈥?Stand-alone MP3 Decoder
鈥?48, 44.1, 32, 24, 22.05, 16 KHz Sampling Frequency
鈥?Separated Digital Volume Control on Left and Right Channels (Software Control
Using 31 Steps)
鈥?Bass, Medium, and Treble Control (31 Steps)
鈥?Bass Boost Sound Effect
鈥?Ancillary Data Extraction
鈥?鈥淐RC Error鈥?and 鈥淢PEG Frame Synchronization鈥?Indicators
Programmable Audio Output for Interfacing With Common Audio DAC
鈥?PCM Format Compatible
鈥?I
2
S Format Compatible
8-bit MCU C51 Core Based (F
MAX
= 20 MHz)
2304 bytes of Internal RAM
64 Kbytes of Code Memory
鈥?Flash: AT89C51SND1A, ROM: AT83C51SND1A
4 Kbytes of Boot Flash Memory (AT89C51SND1A)
鈥?ISP: Download from USB or UART to any External Memory Cards
USB Rev 1.1 Controller
鈥?鈥淔ull Speed鈥?Data Transmission
Built-in PLL
鈥?MP3 Audio Clocks
鈥?USB Clock
MultiMediaCard鈩?Interface Compatibility
Atmel DataFlash鈩?SPI Interface Compatibility
IDE/ATAPI Interface
2 Channels 10-bit ADC, 8 KHz (8 True Bit)
鈥?Battery Voltage Monitoring
鈥?Voice Recording Controlled by Software
Up to 44 bits of General-purpose I/Os for:
鈥?4-bit Interrupt Keyboard Port for a 4 x n Matrix
鈥?Smartmedia鈩?Software Interface
Standard Two 16-bit Timers/Counters
Hardware Watchdog Timer
Standard Full Duplex UART with Baud Rate Generator
2-wire Master and Slave Modes Controller
SPI Master and Slave Modes Controller
Power Management
鈥?Power-on reset
鈥?Software Programmable MCU Clock
鈥?Idle Mode, Power-down Mode
Operating Conditions:
鈥?3V,
鹵10%,
25 mA Typical Operating at 25擄C
鈥?Temperature Range: -40擄C to +85擄C
Packages
鈥?TQFP80, PLCC84 (Development Board)
鈥?Dice
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Single Chip
Microcontroller
with MP3
Decoder and
Man Machine
Interface
AT8xC51SND1A
Preliminary
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Description
The AT8xC51SND1A is a fully integrated stand-alone hardwired MPEGI/II-Layer 3
decoder with a C51 microcontroller core handling data flow and MP3-player control.
The AT89C51SND1A includes 64 Kbytes of Flash memory and allows In-System Pro-
gramming through an embedded 4 Kbytes of Boot Flash Memory.
Rev. 4106E鈥?051鈥?3/02
1
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