鈥?/div>
During UART Reception, Clearing REN May Generate Unexpected IT
SPI Interface - Transmission on Master Mode
SPI Interface - SPI SS pin Limitation on Master/Slave
SPI - SPI Slave Responding in a Multislave Configuration When Not Selected by the
Master and its SPDAT Register Loaded
SPI - SPI Slave Not Responding When Selected and Not Loaded
ALE Disabled Toggles During Internal MOVX
Timer 2 - Baud Rate Generator - No IT When TF2 is Set by Software
Timer 2 - Baud Rate Generator - Long Start Time
SPI Slave Mode/Data Corrupted
32 kHz Oscillator for AT83C51IC2/T80C51ID2 Needs External Feed Back Resistor
RB8 Lost With JBC on SCON
C51 Core 鈥?Bad Exit of Power-down in X2 Mode
80C51 MCUs
AT83C51RB2
AT83C51RC2
AT83C51IC2
AT80C51ID2
Errata Sheet
Errata History
Rev
A
Lot Number
above 00395
1st Prod.
Nov 2001
Trouble List
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11
Errata Descriptions
1. During UART Reception, Clearing REN May Generate Unexpected IT
During UART reception, if the REN bit is cleared between a start bit detection and
the end of reception, the UART will not discard the data (RI is set).
Workaround
Test REN at the beginning of Interrupt routine just after CLR RI, and run the Inter-
rupt routine code only if REN is set.
2. SPI Interface - Transmission on Master Mode
A 9th bit is transmitted by the interface when the clock rate is set on divide by 2
mode and a positive polarity is selected; the SPR2, SPR1, SPR0 bits are cleared
(000) and CPOL = 1 on the SPCON register.
Workaround
Set the clock rate divide by 4 and X2 mode.
3. SPI Interface - SPI SS pin Limitation on Master/Slave
The SS pin of the SPI does not return to an I/O when a One-to-One Master/Slave
intercommunication is performed.
Workaround
No
4. SPI - SPI Slave Responding in a Multislave Configuration When Not
Selected by the Master and its SPDAT Register Loaded
In a multislave configuration, if the master is sending the Sck and the Tx data to all
the slaves, and only one slave is selected, the non-selected slaves respond and
generate the end of the transmission interruption (SPIF) if their SPDAT registers
are loaded before the transmission.
Workaround
No
4242A鈥?051鈥?7/03
1
1
2
3
4
