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AT6005ALV-4QC Datasheet

  • AT6005ALV-4QC

  • Coprocessor Field Programmable Gate Arrays

  • 28頁(yè)

  • ATMEL   ATMEL

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Features
鈥?/div>
High-performance
鈥?System Speeds > 100 MHz
鈥?Flip-flop Toggle Rates > 250 MHz
鈥?1.2 ns/1.5 ns Input Delay
鈥?3.0 ns/6.0 ns Output Delay
Up to 204 User I/Os
Thousands of Registers
Cache Logic
廬
Design
鈥?Complete/Partial In-System Reconfiguration
鈥?No Loss of Data or Machine State
鈥?Adaptive Hardware
Low Voltage and Standard Voltage Operation
鈥?5.0 (V
CC
= 4.75V to 5.25V)
鈥?3.3 (V
CC
= 3.0V to 3.6V)
Automatic Component Generators
鈥?Reusable Custom Hard Macro Functions
Very Low-power Consumption
鈥?Standby Current of 500 碌A(chǔ)/ 200 碌A(chǔ)
鈥?Typical Operating Current of 15 to 170 mA
Programmable Clock Options
鈥?Independently Controlled Column Clocks
鈥?Independently Controlled Column Resets
鈥?Clock Skew Less Than 1 ns Across Chip
Independently Configurable I/O (PCI Compatible)
鈥?TTL/CMOS Input Thresholds
鈥?Open Collector/Tristate Outputs
鈥?Programmable Slew-rate Control
鈥?I/O Drive of 16 mA (combinable to 64 mA)
Easy Migration to Atmel Gate Arrays for High Volume Production
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Coprocessor
Field
Programmable
Gate Arrays
AT6000(LV)
Series
鈥?/div>
鈥?/div>
Description
AT6000 Series SRAM-based Field Programmable Gate Arrays (FPGAs) are ideal for
use as reconfigurable coprocessors and implementing compute-intensive logic.
Supporting system speeds greater than 100 MHz and using a typical operating current
of 15 to 170 mA, AT6000 Series devices are ideal for high-speed, compute-intensive
designs. These FPGAs are designed to implement Cache Logic
廬
, which provides the
user with the ability to implement adaptive hardware and perform hardware
acceleration.
The patented AT6000 Series architecture employs a symmetrical grid of small yet
powerful cells connected to a flexible busing network. Independently controlled clocks
and resets govern every column of cells. The array is surrounded by programmable
I/O.
(continued)
AT6000 Series Field Programmable Gate Arrays
Device
Usable Gates
Cells
Registers (maximum)
I/O (maximum)
Typ. Operating Current (mA)
Cell Rows x Columns
AT6002
6,000
1,024
1,024
96
15 - 30
32 x 32
AT6003
9,000
1,600
1,600
120
25 - 45
40 x 40
AT6005
15,000
3,136
3,136
108
40 - 80
56 x 56
AT6010
30,000
6,400
6,400
204
85 - 170
80 x 80
Rev. 0264F鈥?0/99
1

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