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AT49F002 Datasheet

  • AT49F002

  • 2-Megabit 256K x 8 5-volt Only Flash Memory

  • 20頁

  • ATMEL   ATMEL

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Features
鈥?/div>
Single-voltage Operation
鈥?5V Read
鈥?5V Reprogramming
Fast Read Access Time 鈥?55 ns
Internal Program Control and Timer
Sector Architecture
鈥?One 16K Bytes Boot Block with Programming Lockout
鈥?Two 8K Bytes Parameter Blocks
鈥?Four Main Memory Blocks (One 32K Bytes, Three 64K Bytes)
Fast Erase Cycle Time 鈥?4 Seconds
Byte-by-Byte Programming 鈥?20 碌s/Byte Typical
Hardware Data Protection
DATA Polling for End of Program Detection
Low Power Dissipation
鈥?25 mA Active Current
鈥?100 碌A CMOS Standby Current
Typical 10,000 Write Cycles
Green (Pb/Halide-free) Packaging Option
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2-megabit
(256K x 8)
5-volt Only
Flash Memory
AT49F002A
AT49F002AN
AT49F002AT
AT49F002ANT
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1. Description
The AT49F002A(N)(T) is a 5-volt only in-system reprogrammable Flash memory. Its
2 megabits of memory is organized as 262,144 words by 8 bits. Manufactured with
Atmel鈥檚 advanced nonvolatile CMOS technology, the device offers access times to
55 ns with power dissipation of just 137 mW over the industrial temperature range.
When the device is deselected, the CMOS standby current is less than 100 碌A. For
the AT49F002AN(T) pin 1 for the PLCC package and pin 9 for the TSOP package are
no connect pins.
To allow for simple in-system reprogrammability, the AT49F002A(N)(T) does not
require high input voltages for programming. Five-volt-only commands determine the
read and programming operation of the device. Reading data out of the device is sim-
ilar to reading from an EPROM; it has standard CE, OE, and WE inputs to avoid bus
contention. Reprogramming the AT49F002A(N)(T) is performed by erasing a block of
data and then programming on a byte-by-byte basis. The byte programming time is a
fast 20 碌s. The end of a program cycle can be optionally detected by the DATA polling
feature. Once the end of a byte program cycle has been detected, a new access for a
read or program can begin. The typical number of program and erase cycles is in
excess of 10,000 cycles.
The device is erased by executing the erase command sequence; the device inter-
nally controls the erase operations. There are two 8K byte parameter block sections,
four main memory blocks, and one boot block.
The device has the capability to protect the data in the boot block; this feature is
enabled by a command sequence. The 16K-byte boot block section includes a repro-
gramming lock out feature to provide data integrity. The boot sector is designed to
contain user secure code, and when the feature is enabled, the boot sector is pro-
tected from being reprogrammed.
3354F鈥揊LASH鈥?/05

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    PROTECTIVE GUARD KB SER SQ&RND
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    COVER DUST POLY FOR KB SERIES
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