鈥?20 碌A max. Standby for ALE = V
鈥?29 mW max. Active at 5 MHz for V
鈩?/div>
Programming Algorithm 鈥?50 碌s/Byte (Typical)
CMOS- and TTL-compatible Inputs and Outputs
鈥?JEDEC Standard for LVTTL
Integrated Product Identification Code
Commercial and Industrial Temperature Range
Description
The AT27LV520 is a low-power, high-performance, 524,288-bit one-time programma-
ble read-only memory (OTP EPROM) organized 64K by eight bits. It incorporates
latches for the eight lower order address bits to multiplex with the eight data bits. This
minimizes system chip count, reduces cost, and simplifies the design of multiplexed
bus systems. It requires only one power supply in the range of 3.0V to 3.6V for normal
read mode operation, making it ideal for fast, portable systems using battery power.
Any byte can be accessed in less than 70 ns.
The AT27LV520 is available in 173 mil, 20-lead TSSOP and 300 mil, 20-lead SOIC,
one-time programmable (OTP) plastic packages.
(continued)
512K (64K x 8)
Multiplexed
Addresses/
Outputs
Low-voltage
OTP EPROM
AT27LV520
Pin Configurations
Pin Name
A8 - A15
AD0 - AD7
OE /VPP
ALE
Function
Addresses
Addresses/Outputs
Output Enable/Program Supply
Address Latch Enable
TSSOP Top View
A10
A12
A14
ALE
VCC
OE/VPP
A15
A13
A11
A9
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
A8
AD1
AD3
AD5
AD7
GND
AD6
AD4
AD2
AD0
SOIC Top View
OE/VPP
A15
A13
A11
A9
AD0
AD2
AD4
AD6
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
ALE
A14
A12
A10
A8
AD1
AD3
AD5
AD7
Rev. 0911D鈥?5/00
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