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AT25F1024-10UI-2.7 Datasheet

  • AT25F1024-10UI-2.7

  • SPI Serial EEPROM

  • 17頁

  • ETC

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Features
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Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
20 MHz Clock Rate
Byte Mode and 256-byte Page Mode for Program Operations
Sector Architecture
鈥?Four Sectors with 32K Bytes Each
鈥?128 Pages per Sector
Product Identification Mode
Low-voltage Operation
鈥?2.7 (V
CC
= 2.7V to 3.6V)
Sector Write Protection
鈥?Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for
both Hardware and Software Data Protection
Self-timed Program Cycle (60 碌s/Byte Typical)
Self-timed Sector Erase Cycle (1 second/Sector Typical)
Single Cycle Reprogramming (Erase and Program) for Status Register
High Reliability
鈥?Endurance: 10,000 Write Cycles Typical
8-pin JEDEC SOIC, 8-pad Leadless Array Package, and 8-ball dBGA
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SPI Serial
Memory
1M (131,072 x 8)
AT25F1024
Description
The AT25F1024 provides 1,048,576 bits of serial reprogrammable Flash memory
organized as 131,072 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage operation
are essential. The AT25F1024 is available in space-saving 8-pin JEDEC SOIC, 8-pad
leadless array (LAP), and 8-ball dBGA packages.
Pin Configurations
Pin Name
CS
SCK
SI
SO
GND
VCC
WP
HOLD
Function
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power Supply
Write Protect
Suspends Serial Input
8-ball dBGA
VCC
HOLD
SCK
SI
8
7
6
5
1
2
3
4
8-pin SOIC
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
8-pad LAP
CS
SO
WP
GND
VCC
HOLD
SCK
SI
8
7
6
5
1
2
3
4
CS
SO
WP
GND
Bottom View
Bottom View
Rev. 1440D鈥?2/01
1

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