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AT25020Y1-10YI-2.7 Datasheet

  • AT25020Y1-10YI-2.7

  • EEPROM

  • 19頁

  • ETC

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Features
鈥?/div>
Serial Peripheral Interface (SPI) Compatible
鈥?/div>
Supports SPI Modes 0 (0,0) and 3 (1,1)
鈥?/div>
Low-voltage and Standard-voltage Operation
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?2.7 (V
CC
= 2.7V to 5.5V)
3.0 MHz Clock Rate (5V)
8-byte Page Mode
Block Write Protection
鈥?Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for
Both Hardware and Software Data Protection
Self-timed Write Cycle (10 ms max)
High Reliability
鈥?Endurance: One Million Write Cycles
鈥?Data Retention: 100 Years
Automotive Grade and Extended Temperature Devices Available
8-lead PDIP, 8-lead JEDEC SOIC, 8-lead MAP and 8-lead TAP Packages
SPI Serial
EEPROMs
1K (128 x 8)
2K (256 x 8)
4K (512 x 8)
Description
The AT25010/020/040 provides 1024/2048/4096 bits of serial electrically erasable
programmable read only memory (EEPROM) organized as 128/256/512 words of 8
bits each. The device is optimized for use in many industrial and commercial applica-
tions where low-power and low voltage operation are essential. The AT25010/020/040
is available in space saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead MAP and 8-lead
TAP packages.
The AT25010/020/040 is enabled through the Chip Select pin (CS) and accessed via a
3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa-
rate ERASE cycle is required before WRITE.
BLOCK WRITE protection is enabled by programming the status register with one of
four blocks of write protection. Separate program enable and program disable instruc-
tions are provided for additional data protection. Hardware data protection is provided
via the WP pin to protect against inadvertent write attempts. The HOLD pin may be
used to suspend any serial communication without resetting the serial sequence.
AT25010
AT25020
AT25040
Pin Configurations
Pin Name
CS
SCK
SI
SO
GND
VCC
WP
HOLD
Function
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power Supply
Write Protect
Suspends Serial Input
CS
SO
WP
GND
CS
SO
WP
GND
8-lead PDIP
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
8-lead SOIC
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
8-lead MAP/TAP
VCC
HOLD
SCK
SI
8
7
6
5
1
2
3
4
CS
SO
WP
GND
Bottom View
Rev. 0606J鈥揝EEPR鈥?1/02
1

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