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For Programmable Gate Arrays
Cascadable To Support Additional Configurations or Future Higher-density Arrays
Low-power CMOS EEPROM Process
Programmable Reset Polarity
Available in the Space-efficient Surface-mount PLCC Package
In-System Programmable Via 2-Wire Bus
Emulation of 24CXX Serial EPROMs
Available in 3.3V
鹵
10% LV and 5V
鹵
5% C Versions
Description
The AT17C512/010A and AT17LV512/010A (AT17A Series) FPGA Configuration
EEPROMs (Configurators) provide and easy-to-use, cost-effective configuration
memory for programming Altera FLEX Field Programmable Gate Arrays, FPGA, (the
鈥渄evices鈥?. The AT17A Series is packaged in the popular 20-pin PLCC package. The
AT17A Series family uses a simple serial-access procedure to configure one or more
FPGA devices. The AT17A Series organization supplies enough memory to configure
one or multiple smaller FPGAs. Using a special feature of the AT17A Series, the user
can select the polarity of the reset function by programming an EEPROM byte. The
AT17C/LV512/010A parts generate their own internal clock and can be used as a sys-
tem 鈥渕aster鈥?for loading the FPGA devices.
The Atmel devices also supports a system friendly READY pin and a write protect
mechanism. The READY pin is used to simplify system power-up considerations. The
WP1 pin is used to protect part of the device memory during in-system programming.
The AT17A Series can be programmed with industry standard programmers.
FPGA Serial
Configuration
Memories
AT17C512A
AT17LV512A
AT17C010A
AT17LV010A
Pin Configurations
20-Pin PLCC
NC
DATA
NC
VCC
NC
3
2
1
20
19
nCS
GND
NC
nCASC
NC
9
10
11
12
13
DCLK
WP1
NC
NC
RESET/OE
4
5
6
7
8
18
17
16
15
14
SER_EN
NC
NC
READY
NC
Rev. 0974A鈥?4/98
1