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for Field Programmable Gate Arrays (FPGAs)
Cascadable Read Back to Support Additional Configurations or Future
Higher-density Arrays
Low-power CMOS EEPROM Process
Programmable Reset Polarity
Available in the Space-efficient Surface-mount PLCC Package
In-System Programmable Via 2-wire Bus
Emulation of Atmel鈥檚 AT24CXXX Serial EEPROMs
Available in 3.3V 鹵 5% LV and 5V 鹵 5% C Versions
System-friendly READY Pin
Description
The AT17C020A and AT17LV020A (high-density AT17A Series) FPGA Configuration
EEPROMs (Configurators) provide an easy-to-use, cost-effective configuration mem-
ory for programming Altera FLEX
廬
devices. The AT17A Series is packaged in the
popular 20-lead PLCC. The AT17A Series family uses a simple serial-access proce-
dure to configure one or more FPGA devices. The AT17A Series organization
supplies enough memory to configure one or multiple smaller FPGAs. Using a feature
of the AT17A Series, the user can select the polarity of the reset function by program-
ming internal EEPROM bytes. The AT17A parts generate their own internal clock and
can be used as a system 鈥渕aster鈥?for loading the FPGA devices.
The Atmel devices also support a system-friendly READY pin. The READY pin is used
to simplify system power-up considerations.
The AT17A Series Configurators can be programmed with industry-standard program-
mers, or Atmel鈥檚 ATDH2200E Programming Kit.
FPGA
Configuration
EEPROM
Memory
2-Mbit
Altera Pinout
AT17C020A
AT17LV020A
Pin Configurations
PLCC
NC
DATA
NC
VCC
NC
3
2
1
20
19
nCS
GND
NC
(A2) nCASC
NC
9
10
11
12
13
DCLK
NC
NC
NC
OE
4
5
6
7
8
18
17
16
15
14
SER_EN
NC
NC
READY
NC
Rev. 1270A鈥?5/00
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