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FPGAs
Cascadable Read Back to Support Additional Configurations or Higher-density Arrays
Low-power CMOS EEPROM Process
Programmable Reset Polarity
Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC
Packages), 8-lead PDIP and 20-lead PLCC Packages (Pin Compatible Across Product
Family)
Emulation of Atmel鈥檚 AT24CXXX Serial EEPROMs
Available in 3.3V 鹵 10% LV and 5V 鹵 5% C Versions
System-friendly READY Pin
Low-power Standby Mode
FPGA
Configuration
EEPROM
Memory
512-kilobit and
1-megabit
Description
The AT17C512/010 and AT17LV512/010 (high-density AT17 Series) FPGA
Configuration EEPROMs (Configurators) provide an easy-to-use, cost-effective con-
figuration memory for programming Field Programmable Gate Arrays. The AT17
Series is packaged in the 8-lead LAP, 8-lead PDIP and the popular 20-lead PLCC. The
AT17 Series uses a simple serial-access procedure to configure one or more FPGA
devices. The user can select the polarity of the reset function by programming four
EEPROM bytes. These devices support a write protection mode and a system-friendly
READY pin, which signifies a 鈥済ood鈥?power level to the FPGA and can be used to
ensure reliable system power-up.
The AT17 Series Configurators can be programmed with industry-standard program-
mers, Atmel鈥檚 ATDH2200E Programming Kit or Atmel鈥檚 ATDH2225 ISP Cable.
AT17C512
AT17LV512
AT17C010
AT17LV010
Rev. 0944E鈥?2/01
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